Author: adrian
Date: Sat May 14 04:05:23 2011
New Revision: 221875
URL: http://svn.freebsd.org/changeset/base/221875
Log:
Fixes from the Atheros HAL - formatting; update Merlin checks to be
consistent.
Nothing functional should change with this commit.
Modified:
head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Sat May 14 04:02:56
2011 (r221874)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Sat May 14 04:05:23
2011 (r221875)
@@ -146,7 +146,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMO
/* For chips on which the RTC reset is done, save TSF before it gets
cleared */
if (AR_SREV_HOWL(ah) ||
- (AR_SREV_MERLIN_20_OR_LATER(ah) && ath_hal_eepromGetFlag(ah,
AR_EEP_OL_PWRCTRL)))
+ (AR_SREV_MERLIN(ah) && ath_hal_eepromGetFlag(ah,
AR_EEP_OL_PWRCTRL)))
tsf = ar5212GetTsf64(ah);
/* Mark PHY as inactive; marked active in ar5416InitBB() */
@@ -663,7 +663,7 @@ ar5416ChipReset(struct ath_hal *ah, cons
/*
* Warm reset is optimistic.
*/
- if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
+ if (AR_SREV_MERLIN(ah) &&
ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))
return AH_FALSE;
@@ -1449,7 +1449,7 @@ ar5416SetDefGainValues(struct ath_hal *a
if (IS_EEP_MINOR_V3(ah)) {
txRxAttenLocal = pModal->txRxAttenCh[i];
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
pModal->bswMargin[i]);
@@ -1472,7 +1472,7 @@ ar5416SetDefGainValues(struct ath_hal *a
}
}
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
OS_REG_RMW_FIELD(ah,
AR_PHY_RXGAIN + regChainOffset,
AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
@@ -1551,8 +1551,10 @@ ar5416SetBoardValues(struct ath_hal *ah,
SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
/*
- * Large signal upgrade.
- * XXX update
+ * Large signal upgrade,
+ * If 14.3 or later EEPROM, use
+ * txRxAttenLocal = pModal->txRxAttenCh[i]
+ * else txRxAttenLocal is fixed value above.
*/
if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah))
@@ -1560,7 +1562,7 @@ ar5416SetBoardValues(struct ath_hal *ah,
}
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0,
AR_AN_RF2G1_CH0_OB, pModal->ob);
OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0,
AR_AN_RF2G1_CH0_DB, pModal->db);
@@ -1582,7 +1584,7 @@ ar5416SetBoardValues(struct ath_hal *ah,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
pModal->switchSettling);
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
pModal->adcDesiredSize);
- if (! AR_SREV_MERLIN_20_OR_LATER(ah))
+ if (! AR_SREV_MERLIN_10_OR_LATER(ah))
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA,
pModal->pgaDesiredSize);
OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
@@ -1591,7 +1593,8 @@ ar5416SetBoardValues(struct ath_hal *ah,
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
- OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
pModal->txEndToRxOn);
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
+ pModal->txEndToRxOn);
if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
@@ -1607,27 +1610,36 @@ ar5416SetBoardValues(struct ath_hal *ah,
/* Minor Version Specific application */
if (IS_EEP_MINOR_V2(ah)) {
- OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
pModal->txFrameToDataStart);
- OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
pModal->txFrameToPaOn);
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
+ pModal->txFrameToDataStart);
+ OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
+ pModal->txFrameToPaOn);
}
if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan))
/* Overwrite switch settling with HT40 value */
- OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
pModal->swSettleHt40);
+ OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
+ pModal->swSettleHt40);
if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >=
AR5416_EEP_MINOR_VER_19)
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);
if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20)
{
if (IEEE80211_IS_CHAN_2GHZ(chan))
- OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1,
AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
+ OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1,
AR_AN_TOP1_DACIPMODE,
+ eep->baseEepHeader.dacLpMode);
else if (eep->baseEepHeader.dacHiPwrMode_5G)
OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1,
AR_AN_TOP1_DACIPMODE, 0);
else
- OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1,
AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
+ OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1,
AR_AN_TOP1_DACIPMODE,
+ eep->baseEepHeader.dacLpMode);
+
+ OS_DELAY(100);
- OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
AR_PHY_FRAME_CTL_TX_CLIP, pModal->miscBits >> 2);
- OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK);
+ OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
AR_PHY_FRAME_CTL_TX_CLIP,
+ pModal->miscBits >> 2);
+ OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
AR_PHY_TX_DESIRED_SCALE_CCK,
+ eep->baseEepHeader.desiredScaleCCK);
}
return AH_TRUE;
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c Sat May 14 04:02:56
2011 (r221874)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c Sat May 14 04:05:23
2011 (r221875)
@@ -99,6 +99,10 @@ ar9280AniSetup(struct ath_hal *ah)
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
+/* XXX shouldn't be here! */
+#define EEP_MINOR(_ah) \
+ (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
+
/*
* Attach for an AR9280 part.
*/
@@ -270,7 +274,8 @@ ar9280Attach(uint16_t devid, HAL_SOFTC s
ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM
pwr offset: %d dBm; curves will be adjusted.\n",
AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+ /* XXX check for >= minor ver 17 */
+ if (AR_SREV_MERLIN_20(ah)) {
/* setup rxgain table */
switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) {
case AR5416_EEP_RXGAIN_13dB_BACKOFF:
@@ -290,7 +295,9 @@ ar9280Attach(uint16_t devid, HAL_SOFTC s
goto bad; /* XXX ? try to continue */
}
}
- if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+
+ /* XXX check for >= minor ver 19 */
+ if (AR_SREV_MERLIN_20(ah)) {
/* setp txgain table */
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
case AR5416_EEP_TXGAIN_HIGH_POWER:
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