Author: kib
Date: Thu Jul 2 10:44:45 2020
New Revision: 362887
URL: https://svnweb.freebsd.org/changeset/base/362887
Log:
mlx5_core: remove unneccessary LFENCE instruction.
Use fence instead of barrier, which is optimized to take advantage of
the x86 TSO memory model.
Reviewed by: hselasky
Sponsored by: Mellanox Technologies
MFC after: 1 week
Modified:
head/sys/dev/mlx5/mlx5_core/mlx5_eq.c
Modified: head/sys/dev/mlx5/mlx5_core/mlx5_eq.c
==============================================================================
--- head/sys/dev/mlx5/mlx5_core/mlx5_eq.c Thu Jul 2 10:42:58 2020
(r362886)
+++ head/sys/dev/mlx5/mlx5_core/mlx5_eq.c Thu Jul 2 10:44:45 2020
(r362887)
@@ -240,7 +240,7 @@ static int mlx5_eq_int(struct mlx5_core_dev *dev, stru
* Make sure we read EQ entry contents after we've
* checked the ownership bit.
*/
- rmb();
+ atomic_thread_fence_acq();
mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
eq->eqn, eqe_type_str(eqe->type));
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