Author: imp
Date: Thu Apr 30 00:43:02 2020
New Revision: 360483
URL: https://svnweb.freebsd.org/changeset/base/360483
Log:
Return the nvmeX device associated with the ndaX device.
Add the nvmeX device to the XPT_PATH_INQ nvme specific
information. while one could figure this out by looking up the
domain:bus:slot:function, it's a lot easier to have the SIM set it
directly since the sim knows this.
Modified:
head/sys/cam/cam_ccb.h
head/sys/dev/nvme/nvme_sim.c
Modified: head/sys/cam/cam_ccb.h
==============================================================================
--- head/sys/cam/cam_ccb.h Thu Apr 30 00:27:19 2020 (r360482)
+++ head/sys/cam/cam_ccb.h Thu Apr 30 00:43:02 2020 (r360483)
@@ -630,6 +630,7 @@ struct ccb_pathinq_settings_sas {
u_int32_t bitrate; /* Mbps */
};
+#define NVME_DEV_NAME_LEN 52
struct ccb_pathinq_settings_nvme {
uint32_t nsid; /* Namespace ID for this path */
uint32_t domain;
@@ -637,7 +638,10 @@ struct ccb_pathinq_settings_nvme {
uint8_t slot;
uint8_t function;
uint8_t extra;
+ char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for
this device */
};
+_Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64,
+ "ccb_pathinq_settings_nvme too big");
#define PATHINQ_SETTINGS_SIZE 128
@@ -1030,6 +1034,7 @@ struct ccb_trans_settings_nvme
uint8_t speed; /* PCIe generation for each lane */
uint8_t max_lanes; /* Number of PCIe lanes */
uint8_t max_speed; /* PCIe generation for each lane */
+
};
#include <cam/mmc/mmc_bus.h>
Modified: head/sys/dev/nvme/nvme_sim.c
==============================================================================
--- head/sys/dev/nvme/nvme_sim.c Thu Apr 30 00:27:19 2020
(r360482)
+++ head/sys/dev/nvme/nvme_sim.c Thu Apr 30 00:43:02 2020
(r360483)
@@ -203,6 +203,8 @@ nvme_sim_action(struct cam_sim *sim, union ccb *ccb)
cpi->xport_specific.nvme.slot = pci_get_slot(dev);
cpi->xport_specific.nvme.function = pci_get_function(dev);
cpi->xport_specific.nvme.extra = 0;
+ strncpy(cpi->xport_specific.nvme.dev_name,
device_get_nameunit(ctrlr->dev),
+ sizeof(cpi->xport_specific.nvme.dev_name));
cpi->ccb_h.status = CAM_REQ_CMP;
break;
}
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