Author: mmacy
Date: Fri Apr 3 22:36:22 2020
New Revision: 359622
URL: https://svnweb.freebsd.org/changeset/base/359622
Log:
Update x86 counters
MFC after: 1 week
Added:
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/cache.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/clx-metrics.json
(contents, props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/floating-point.json
(contents, props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/frontend.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/memory.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/other.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/pipeline.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/uncore-memory.json
(contents, props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/uncore-other.json
(contents, props changed)
head/lib/libpmc/pmu-events/arch/x86/cascadelakex/virtual-memory.json
(contents, props changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/
head/lib/libpmc/pmu-events/arch/x86/icelake/cache.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/floating-point.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/frontend.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/memory.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/other.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/pipeline.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/icelake/virtual-memory.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/silvermont/other.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/
head/lib/libpmc/pmu-events/arch/x86/tremontx/cache.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/frontend.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/memory.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/other.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/pipeline.json (contents, props
changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/uncore-memory.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/uncore-other.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/uncore-power.json (contents,
props changed)
head/lib/libpmc/pmu-events/arch/x86/tremontx/virtual-memory.json (contents,
props changed)
Modified:
head/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json
head/lib/libpmc/pmu-events/arch/x86/bonnell/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/cache.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/floating-point.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/frontend.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/memory.json
head/lib/libpmc/pmu-events/arch/x86/broadwell/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
head/lib/libpmc/pmu-events/arch/x86/broadwellde/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/broadwellx/bdx-metrics.json
head/lib/libpmc/pmu-events/arch/x86/broadwellx/cache.json
head/lib/libpmc/pmu-events/arch/x86/broadwellx/floating-point.json
head/lib/libpmc/pmu-events/arch/x86/broadwellx/memory.json
head/lib/libpmc/pmu-events/arch/x86/broadwellx/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/goldmont/cache.json
head/lib/libpmc/pmu-events/arch/x86/goldmont/memory.json
head/lib/libpmc/pmu-events/arch/x86/goldmont/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/goldmont/virtual-memory.json
head/lib/libpmc/pmu-events/arch/x86/goldmontplus/cache.json
head/lib/libpmc/pmu-events/arch/x86/goldmontplus/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/goldmontplus/virtual-memory.json
head/lib/libpmc/pmu-events/arch/x86/haswell/cache.json
head/lib/libpmc/pmu-events/arch/x86/haswell/floating-point.json
head/lib/libpmc/pmu-events/arch/x86/haswell/hsw-metrics.json
head/lib/libpmc/pmu-events/arch/x86/haswell/memory.json
head/lib/libpmc/pmu-events/arch/x86/haswell/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/haswellx/cache.json
head/lib/libpmc/pmu-events/arch/x86/haswellx/hsx-metrics.json
head/lib/libpmc/pmu-events/arch/x86/haswellx/memory.json
head/lib/libpmc/pmu-events/arch/x86/haswellx/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/ivybridge/cache.json
head/lib/libpmc/pmu-events/arch/x86/ivybridge/ivb-metrics.json
head/lib/libpmc/pmu-events/arch/x86/ivybridge/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/ivytown/ivt-metrics.json
head/lib/libpmc/pmu-events/arch/x86/ivytown/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/ivytown/uncore-power.json
head/lib/libpmc/pmu-events/arch/x86/jaketown/cache.json
head/lib/libpmc/pmu-events/arch/x86/jaketown/jkt-metrics.json
head/lib/libpmc/pmu-events/arch/x86/jaketown/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/jaketown/uncore-power.json
head/lib/libpmc/pmu-events/arch/x86/knightslanding/cache.json
head/lib/libpmc/pmu-events/arch/x86/knightslanding/memory.json
head/lib/libpmc/pmu-events/arch/x86/knightslanding/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/knightslanding/virtual-memory.json
head/lib/libpmc/pmu-events/arch/x86/mapfile.csv
head/lib/libpmc/pmu-events/arch/x86/sandybridge/cache.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/floating-point.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/frontend.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/memory.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/other.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/snb-metrics.json
head/lib/libpmc/pmu-events/arch/x86/sandybridge/virtual-memory.json
head/lib/libpmc/pmu-events/arch/x86/silvermont/cache.json
head/lib/libpmc/pmu-events/arch/x86/silvermont/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/skylake/cache.json
head/lib/libpmc/pmu-events/arch/x86/skylake/frontend.json
head/lib/libpmc/pmu-events/arch/x86/skylake/memory.json
head/lib/libpmc/pmu-events/arch/x86/skylake/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/skylake/skl-metrics.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/cache.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/floating-point.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/frontend.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/memory.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/pipeline.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/skx-metrics.json
head/lib/libpmc/pmu-events/arch/x86/skylakex/uncore-other.json
Modified: head/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json Fri Apr 3
22:22:50 2020 (r359621)
+++ head/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json Fri Apr 3
22:36:22 2020 (r359622)
@@ -77,7 +77,7 @@
"UMask": "0x1",
"EventName": "UOPS.MS_CYCLES",
"SampleAfterValue": "2000000",
- "BriefDescription": "This event counts the cycles where 1 or more uops
are issued by the micro-sequencer (MS), including microcode assists and
inserted flows, and written to the IQ. ",
+ "BriefDescription": "This event counts the cycles where 1 or more uops
are issued by the micro-sequencer (MS), including microcode assists and
inserted flows, and written to the IQ.",
"CounterMask": "1"
}
]
\ No newline at end of file
Modified: head/lib/libpmc/pmu-events/arch/x86/bonnell/pipeline.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/bonnell/pipeline.json Fri Apr 3
22:22:50 2020 (r359621)
+++ head/lib/libpmc/pmu-events/arch/x86/bonnell/pipeline.json Fri Apr 3
22:36:22 2020 (r359622)
@@ -189,7 +189,7 @@
"UMask": "0x8",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
- "BriefDescription": "Mispredicted indirect calls, including both
register and memory indirect. "
+ "BriefDescription": "Mispredicted indirect calls, including both
register and memory indirect."
},
{
"EventCode": "0x89",
Modified: head/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json Fri Apr
3 22:22:50 2020 (r359621)
+++ head/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json Fri Apr
3 22:36:22 2020 (r359622)
@@ -1,6 +1,62 @@
[
{
- "BriefDescription": "Instructions Per Cycle (per logical thread)",
+ "BriefDescription": "This category represents fraction of slots where
the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)",
+ "MetricGroup": "TopdownL1",
+ "MetricName": "Frontend_Bound",
+ "PublicDescription": "This category represents fraction of slots where
the processor's Frontend undersupplies its Backend. Frontend denotes the first
part of the processor core responsible to fetch operations that are executed
later on by the Backend part. Within the Frontend; a branch predictor predicts
the next address to fetch; cache-lines are fetched from the memory subsystem;
parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the
Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes
unutilized issue-slots when there is no Backend stall; i.e. bubbles where
Frontend delivered no uops while Backend could have accepted them. For example;
stalls due to instruction-cache misses would be categorized under Frontend
Bound."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where
the processor's Frontend undersupplies its Backend. SMT version; use when SMT
is enabled and measuring per logical CPU.",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))",
+ "MetricGroup": "TopdownL1_SMT",
+ "MetricName": "Frontend_Bound_SMT",
+ "PublicDescription": "This category represents fraction of slots where
the processor's Frontend undersupplies its Backend. Frontend denotes the first
part of the processor core responsible to fetch operations that are executed
later on by the Backend part. Within the Frontend; a branch predictor predicts
the next address to fetch; cache-lines are fetched from the memory subsystem;
parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the
Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes
unutilized issue-slots when there is no Backend stall; i.e. bubbles where
Frontend delivered no uops while Backend could have accepted them. For example;
stalls due to instruction-cache misses would be categorized under Frontend
Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots wasted
due to incorrect speculations",
+ "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 *
INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)",
+ "MetricGroup": "TopdownL1",
+ "MetricName": "Bad_Speculation",
+ "PublicDescription": "This category represents fraction of slots
wasted due to incorrect speculations. This include slots used to issue uops
that do not eventually get retired and slots for which the issue-pipeline was
blocked due to recovery from earlier incorrect speculation. For example; wasted
work due to miss-predicted branches are categorized under Bad Speculation
category. Incorrect data speculation followed by Memory Ordering Nukes is
another example."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots wasted
due to incorrect speculations. SMT version; use when SMT is enabled and
measuring per logical CPU.",
+ "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((
INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 )
* ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))",
+ "MetricGroup": "TopdownL1_SMT",
+ "MetricName": "Bad_Speculation_SMT",
+ "PublicDescription": "This category represents fraction of slots
wasted due to incorrect speculations. This include slots used to issue uops
that do not eventually get retired and slots for which the issue-pipeline was
blocked due to recovery from earlier incorrect speculation. For example; wasted
work due to miss-predicted branches are categorized under Bad Speculation
category. Incorrect data speculation followed by Memory Ordering Nukes is
another example. SMT version; use when SMT is enabled and measuring per logical
CPU."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where
no uops are being delivered due to a lack of required resources for accepting
new uops in the Backend",
+ "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + ((
UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) /
(4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )",
+ "MetricGroup": "TopdownL1",
+ "MetricName": "Backend_Bound",
+ "PublicDescription": "This category represents fraction of slots where
no uops are being delivered due to a lack of required resources for accepting
new uops in the Backend. Backend is the portion of the processor core where the
out-of-order scheduler dispatches ready uops into their respective execution
units; and once completed these uops get retired according to program order.
For example; stalls due to data-cache misses or stalls due to the divider unit
being overloaded are both categorized under Backend Bound. Backend Bound is
further divided into two main categories: Memory Bound and Core Bound."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots where
no uops are being delivered due to a lack of required resources for accepting
new uops in the Backend. SMT version; use when SMT is enabled and measuring per
logical CPU.",
+ "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY -
UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 *
(( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))) )",
+ "MetricGroup": "TopdownL1_SMT",
+ "MetricName": "Backend_Bound_SMT",
+ "PublicDescription": "This category represents fraction of slots where
no uops are being delivered due to a lack of required resources for accepting
new uops in the Backend. Backend is the portion of the processor core where the
out-of-order scheduler dispatches ready uops into their respective execution
units; and once completed these uops get retired according to program order.
For example; stalls due to data-cache misses or stalls due to the divider unit
being overloaded are both categorized under Backend Bound. Backend Bound is
further divided into two main categories: Memory Bound and Core Bound. SMT
version; use when SMT is enabled and measuring per logical CPU."
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots
utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)",
+ "MetricGroup": "TopdownL1",
+ "MetricName": "Retiring",
+ "PublicDescription": "This category represents fraction of slots
utilized by useful work i.e. issued uops that eventually get retired. Ideally;
all pipeline slots would be attributed to the Retiring category. Retiring of
100% would indicate the maximum 4 uops retired per cycle has been achieved.
Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note
that a high Retiring value does not necessary mean there is no room for more
performance. For example; Microcode assists are categorized under Retiring.
They hurt performance and can often be avoided. "
+ },
+ {
+ "BriefDescription": "This category represents fraction of slots
utilized by useful work i.e. issued uops that eventually get retired. SMT
version; use when SMT is enabled and measuring per logical CPU.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))",
+ "MetricGroup": "TopdownL1_SMT",
+ "MetricName": "Retiring_SMT",
+ "PublicDescription": "This category represents fraction of slots
utilized by useful work i.e. issued uops that eventually get retired. Ideally;
all pipeline slots would be attributed to the Retiring category. Retiring of
100% would indicate the maximum 4 uops retired per cycle has been achieved.
Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note
that a high Retiring value does not necessary mean there is no room for more
performance. For example; Microcode assists are categorized under Retiring.
They hurt performance and can often be avoided. SMT version; use when SMT is
enabled and measuring per logical CPU."
+ },
+ {
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1",
"MetricName": "IPC"
@@ -8,40 +64,82 @@
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline",
+ "MetricGroup": "Pipeline;Retire",
"MetricName": "UPI"
},
{
- "BriefDescription": "Rough Estimation of fraction of fetched lines
bytes that were likely consumed by program instructions",
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fetch_BW;PGO",
+ "MetricName": "IpTB"
+ },
+ {
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES /
BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;PGO",
+ "MetricName": "BpTB"
+ },
+ {
+ "BriefDescription": "Rough Estimation of fraction of fetched lines
bytes that were likely (includes speculatively fetches) consumed by program
instructions",
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS /
INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
- "MetricGroup": "Frontend",
+ "MetricGroup": "PGO;IcMiss",
"MetricName": "IFetch_Line_Utilization"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka
Decoded Icache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS +
IDQ.MITE_UOPS + IDQ.MS_UOPS )",
- "MetricGroup": "DSB; Frontend_Bandwidth",
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka
Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS +
IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
+ "MetricGroup": "DSB;Fetch_BW",
"MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "Cycles Per Instruction (threaded)",
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
"MetricGroup": "Pipeline;Summary",
"MetricName": "CPI"
},
{
- "BriefDescription": "Per-thread actual clocks when the logical
processor is active. This is called 'Clockticks' in VTune.",
+ "BriefDescription": "Per-Logical Processor actual clocks when the
Logical Processor is active.",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary",
"MetricName": "CLKS"
},
{
- "BriefDescription": "Total issue-pipeline slots",
- "MetricExpr": "4*(( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else
cycles)",
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
+ "MetricExpr": "4 * cycles",
"MetricGroup": "TopDownL1",
"MetricName": "SLOTS"
},
{
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core)",
+ "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 +
CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
+ "MetricGroup": "TopDownL1_SMT",
+ "MetricName": "SLOTS_SMT"
+ },
+ {
+ "BriefDescription": "Instructions per Load (lower number means higher
occurance rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+ "MetricGroup": "Instruction_Type",
+ "MetricName": "IpL"
+ },
+ {
+ "BriefDescription": "Instructions per Store (lower number means higher
occurance rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+ "MetricGroup": "Instruction_Type",
+ "MetricName": "IpS"
+ },
+ {
+ "BriefDescription": "Instructions per Branch (lower number means
higher occurance rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Instruction_Type",
+ "MetricName": "IpB"
+ },
+ {
+ "BriefDescription": "Instruction per (near) call (lower number means
higher occurance rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches",
+ "MetricName": "IpCall"
+ },
+ {
"BriefDescription": "Total number of retired Instructions",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary",
@@ -49,47 +147,131 @@
},
{
"BriefDescription": "Instructions Per Cycle (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / (( CPU_CLK_UNHALTED.THREAD_ANY / 2 )
if #SMT_on else cycles)",
+ "MetricExpr": "INST_RETIRED.ANY / cycles",
"MetricGroup": "SMT",
"MetricName": "CoreIPC"
},
{
+ "BriefDescription": "Instructions Per Cycle (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) *
( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
+ "MetricGroup": "SMT",
+ "MetricName": "CoreIPC_SMT"
+ },
+ {
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE +
FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 *
FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (
FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE +
FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 *
FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles",
+ "MetricGroup": "FLOPS",
+ "MetricName": "FLOPc"
+ },
+ {
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE +
FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 *
FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (
FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE +
FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 *
FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2
) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
+ "MetricGroup": "FLOPS_SMT",
+ "MetricName": "FLOPc_SMT"
+ },
+ {
"BriefDescription": "Instruction-Level-Parallelism (average number of
uops executed when there is at least 1 uop executed)",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((
cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else
UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
- "MetricGroup": "Pipeline;Ports_Utilization",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / ((
cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else
UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricGroup": "Pipeline",
"MetricName": "ILP"
},
{
- "BriefDescription": "Average Branch Address Clear Cost (fraction of
cycles)",
- "MetricExpr": "2* (( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL -
(( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*
ITLB_MISSES.WALK_COMPLETED )) ) / RS_EVENTS.EMPTY_END)",
- "MetricGroup": "Unknown_Branches",
- "MetricName": "BAClear_Cost"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown
slots wasted per non-speculative branch misprediction (jeclear)",
+ "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / (
BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY -
UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) +
(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * (
BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles)
/ (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 *
cycles) / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "Core actual clocks when any thread is active on
the physical core",
- "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else
CPU_CLK_UNHALTED.THREAD",
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown
slots wasted per non-speculative branch misprediction (jeclear)",
+ "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / (
BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY -
UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 *
(( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 *
IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES +
MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 *
IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( (
CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE /
CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) *
( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) /
BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "BrMispredicts_SMT",
+ "MetricName": "Branch_Misprediction_Cost_SMT"
+ },
+ {
+ "BriefDescription": "Number of Instructions per non-speculative Branch
Misprediction (JEClear)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "BrMispredicts",
+ "MetricName": "IpMispredict"
+ },
+ {
+ "BriefDescription": "Core actual clocks when any Logical Processor is
active on the Physical Core",
+ "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 +
CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss
demand loads",
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss
demand loads (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS
+ mem_load_uops_retired.hit_lfb )",
"MetricGroup": "Memory_Bound;Memory_Lat",
"MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1
miss demand load when there is at least 1 such miss)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / ((
cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else
L1D_PEND_MISS.PENDING_CYCLES)",
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1
miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
"MetricGroup": "Memory_Bound;Memory_BW",
"MetricName": "MLP"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving
STLB misses triggered by instruction/Load/Store accesses",
- "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ +
7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED))
/ (( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
+ "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * (
DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED +
ITLB_MISSES.WALK_COMPLETED ) ) / cycles",
"MetricGroup": "TLB",
"MetricName": "Page_Walks_Utilization"
},
{
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving
STLB misses triggered by instruction/Load/Store accesses",
+ "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ +
cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * (
DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED +
ITLB_MISSES.WALK_COMPLETED ) ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 +
CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
+ "MetricGroup": "TLB_SMT",
+ "MetricName": "Page_Walks_Utilization_SMT"
+ },
+ {
+ "BriefDescription": "Average data fill bandwidth to the L1 data cache
[GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricGroup": "Memory_BW",
+ "MetricName": "L1D_Cache_Fill_BW"
+ },
+ {
+ "BriefDescription": "Average data fill bandwidth to the L2 cache [GB /
sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricGroup": "Memory_BW",
+ "MetricName": "L2_Cache_Fill_BW"
+ },
+ {
+ "BriefDescription": "Average per-core data fill bandwidth to the L3
cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 /
duration_time",
+ "MetricGroup": "Memory_BW",
+ "MetricName": "L3_Cache_Fill_BW"
+ },
+ {
+ "BriefDescription": "L1 cache true misses per kilo instruction for
retired demand loads",
+ "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS /
INST_RETIRED.ANY",
+ "MetricGroup": "Cache_Misses",
+ "MetricName": "L1MPKI"
+ },
+ {
+ "BriefDescription": "L2 cache true misses per kilo instruction for
retired demand loads",
+ "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS /
INST_RETIRED.ANY",
+ "MetricGroup": "Cache_Misses",
+ "MetricName": "L2MPKI"
+ },
+ {
+ "BriefDescription": "L2 cache misses per kilo instruction for all
request types (including speculative)",
+ "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Cache_Misses",
+ "MetricName": "L2MPKI_All"
+ },
+ {
+ "BriefDescription": "L2 cache hits per kilo instruction for all
request types (including speculative)",
+ "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) /
INST_RETIRED.ANY",
+ "MetricGroup": "Cache_Misses",
+ "MetricName": "L2HPKI_All"
+ },
+ {
+ "BriefDescription": "L3 cache true misses per kilo instruction for
retired demand loads",
+ "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS /
INST_RETIRED.ANY",
+ "MetricGroup": "Cache_Misses",
+ "MetricName": "L3MPKI"
+ },
+ {
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricGroup": "Summary",
@@ -97,7 +279,7 @@
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "(( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE +
FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2*
FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*(
FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE +
FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8*
FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 / duration_time",
+ "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE +
FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 *
FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (
FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE +
FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 *
FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time",
"MetricGroup": "FLOPS;Summary",
"MetricName": "GFLOPs"
},
@@ -108,16 +290,22 @@
"MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "Fraction of cycles where both hardware threads
were active",
+ "BriefDescription": "Fraction of cycles where both hardware Logical
Processors were active",
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / (
CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT;Summary",
"MetricName": "SMT_2T_Utilization"
},
{
"BriefDescription": "Fraction of cycles spent in Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:u / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:k / CPU_CLK_UNHALTED.REF_TSC",
"MetricGroup": "Summary",
"MetricName": "Kernel_Utilization"
+ },
+ {
+ "BriefDescription": "Average external Memory Bandwidth Use for reads
and writes [GB / sec]",
+ "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ +
arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
+ "MetricGroup": "Memory_BW",
+ "MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "C3 residency percent per core",
Modified: head/lib/libpmc/pmu-events/arch/x86/broadwell/cache.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/x86/broadwell/cache.json Fri Apr 3
22:22:50 2020 (r359621)
+++ head/lib/libpmc/pmu-events/arch/x86/broadwell/cache.json Fri Apr 3
22:36:22 2020 (r359622)
@@ -56,10 +56,10 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
- "PublicDescription": "This event counts the number of demand Data Read
requests that hit L2 cache. Only not rejected loads are counted.",
+ "PublicDescription": "Counts the number of demand Data Read requests,
initiated by load instructions, that hit L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
- "UMask": "0x41",
+ "UMask": "0xc1",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Demand Data Read requests that hit L2 cache",
@@ -68,7 +68,7 @@
{
"EventCode": "0x24",
"Counter": "0,1,2,3",
- "UMask": "0x42",
+ "UMask": "0xc2",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "RFO requests that hit L2 cache.",
@@ -77,7 +77,7 @@
{
"EventCode": "0x24",
"Counter": "0,1,2,3",
- "UMask": "0x44",
+ "UMask": "0xc4",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "L2 cache hits when fetching instructions, code
reads.",
@@ -87,7 +87,7 @@
"PublicDescription": "This event counts the number of requests from
the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
- "UMask": "0x50",
+ "UMask": "0xd0",
"EventName": "L2_RQSTS.L2_PF_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "L2 prefetch requests that hit L2 cache",
@@ -771,2628 +771,2628 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
- "PublicDescription": "Counts demand data reads that have any response
type. Offcore response can be programmed only with a specific pair of event
select and counter MSR, and with specific event codes and predefine mask bit
value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts demand data reads have any response
type.",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0000010001 ",
+ "MSRValue": "0x0000010001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that have any response
type.",
+ "BriefDescription": "Counts demand data reads have any response type.",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0080020001 ",
+ "MSRValue": "0x0080020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0100020001 ",
+ "MSRValue": "0x0100020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE &
SNOOP_NOT_NEEDED",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0200020001 ",
+ "MSRValue": "0x0200020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0400020001 ",
+ "MSRValue": "0x0400020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE &
SNOOP_HIT_NO_FWD",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x1000020001 ",
+ "MSRValue": "0x1000020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x3f80020001 ",
+ "MSRValue": "0x3F80020001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts demand data reads that hit in the L3 with
no details on snoop-related information. Offcore response can be programmed
only with a specific pair of event select and counter MSR, and with specific
event codes and predefine mask bit value in a dedicated MSR to specify
attributes of the offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x00803c0001 ",
+ "MSRValue": "0x00803C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that hit in the L3 with
no details on snoop-related information.",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts demand data reads that hit in the L3 and
sibling core snoops are not needed as either the core-valid bit is not set or
the shared line is present in multiple cores. Offcore response can be
programmed only with a specific pair of event select and counter MSR, and with
specific event codes and predefine mask bit value in a dedicated MSR to specify
attributes of the offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x01003c0001 ",
+ "MSRValue": "0x01003C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that hit in the L3 and
sibling core snoops are not needed as either the core-valid bit is not set or
the shared line is present in multiple cores.",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts demand data reads that hit in the L3 with
a snoop miss response. Offcore response can be programmed only with a specific
pair of event select and counter MSR, and with specific event codes and
predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x02003c0001 ",
+ "MSRValue": "0x02003C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that hit in the L3 with
a snoop miss response.",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts demand data reads that hit in the L3 and
the snoops to sibling cores hit in either E/S state and the line is not
forwarded. Offcore response can be programmed only with a specific pair of
event select and counter MSR, and with specific event codes and predefine mask
bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x04003c0001 ",
+ "MSRValue": "0x04003C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that hit in the L3 and
the snoops to sibling cores hit in either E/S state and the line is not
forwarded.",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x10003c0001 ",
+ "MSRValue": "0x10003C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts demand data reads that hit in the L3.
Offcore response can be programmed only with a specific pair of event select
and counter MSR, and with specific event codes and predefine mask bit value in
a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts demand data reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x3f803c0001 ",
+ "MSRValue": "0x3F803C0001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts demand data reads that hit in the L3.",
+ "BriefDescription": "Counts demand data reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that have
any response type. Offcore response can be programmed only with a specific pair
of event select and counter MSR, and with specific event codes and predefine
mask bit value in a dedicated MSR to specify attributes of the offcore
transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs) have any
response type.",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0000010002 ",
+ "MSRValue": "0x0000010002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that have
any response type.",
+ "BriefDescription": "Counts all demand data writes (RFOs) have any
response type.",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that hit in
the L3 with no details on snoop-related information. Offcore response can be
programmed only with a specific pair of event select and counter MSR, and with
specific event codes and predefine mask bit value in a dedicated MSR to specify
attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x00803c0002 ",
+ "MSRValue": "0x00803C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that hit in
the L3 with no details on snoop-related information.",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that hit in
the L3 and sibling core snoops are not needed as either the core-valid bit is
not set or the shared line is present in multiple cores. Offcore response can
be programmed only with a specific pair of event select and counter MSR, and
with specific event codes and predefine mask bit value in a dedicated MSR to
specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x01003c0002 ",
+ "MSRValue": "0x01003C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that hit in
the L3 and sibling core snoops are not needed as either the core-valid bit is
not set or the shared line is present in multiple cores.",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that hit in
the L3 with a snoop miss response. Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x02003c0002 ",
+ "MSRValue": "0x02003C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that hit in
the L3 with a snoop miss response.",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that hit in
the L3 and the snoops to sibling cores hit in either E/S state and the line is
not forwarded. Offcore response can be programmed only with a specific pair of
event select and counter MSR, and with specific event codes and predefine mask
bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x04003c0002 ",
+ "MSRValue": "0x04003C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that hit in
the L3 and the snoops to sibling cores hit in either E/S state and the line is
not forwarded.",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x10003c0002 ",
+ "MSRValue": "0x10003C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_HITM",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand data writes (RFOs) that hit in
the L3. Offcore response can be programmed only with a specific pair of event
select and counter MSR, and with specific event codes and predefine mask bit
value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand data writes (RFOs)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x3f803c0002 ",
+ "MSRValue": "0x3F803C0002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand data writes (RFOs) that hit in
the L3.",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that have any
response type. Offcore response can be programmed only with a specific pair of
event select and counter MSR, and with specific event codes and predefine mask
bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand code reads have any response
type.",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0000010004 ",
+ "MSRValue": "0x0000010004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that have any
response type.",
+ "BriefDescription": "Counts all demand code reads have any response
type.",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0080020004 ",
+ "MSRValue": "0x0080020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NONE",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0100020004 ",
+ "MSRValue": "0x0100020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE &
SNOOP_NOT_NEEDED",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0200020004 ",
+ "MSRValue": "0x0200020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_MISS",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0400020004 ",
+ "MSRValue": "0x0400020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE &
SNOOP_HIT_NO_FWD",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x1000020004 ",
+ "MSRValue": "0x1000020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName":
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HITM",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x3f80020004 ",
+ "MSRValue": "0x3F80020004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that hit in the L3
with no details on snoop-related information. Offcore response can be
programmed only with a specific pair of event select and counter MSR, and with
specific event codes and predefine mask bit value in a dedicated MSR to specify
attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x00803c0004 ",
+ "MSRValue": "0x00803C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that hit in the L3
with no details on snoop-related information.",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that hit in the L3
and sibling core snoops are not needed as either the core-valid bit is not set
or the shared line is present in multiple cores. Offcore response can be
programmed only with a specific pair of event select and counter MSR, and with
specific event codes and predefine mask bit value in a dedicated MSR to specify
attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x01003c0004 ",
+ "MSRValue": "0x01003C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that hit in the L3
and sibling core snoops are not needed as either the core-valid bit is not set
or the shared line is present in multiple cores.",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that hit in the L3
with a snoop miss response. Offcore response can be programmed only with a
specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x02003c0004 ",
+ "MSRValue": "0x02003C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that hit in the L3
with a snoop miss response.",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that hit in the L3
and the snoops to sibling cores hit in either E/S state and the line is not
forwarded. Offcore response can be programmed only with a specific pair of
event select and counter MSR, and with specific event codes and predefine mask
bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x04003c0004 ",
+ "MSRValue": "0x04003C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that hit in the L3
and the snoops to sibling cores hit in either E/S state and the line is not
forwarded.",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x10003c0004 ",
+ "MSRValue": "0x10003C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_HITM",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts all demand code reads that hit in the L3.
Offcore response can be programmed only with a specific pair of event select
and counter MSR, and with specific event codes and predefine mask bit value in
a dedicated MSR to specify attributes of the offcore transaction.",
+ "PublicDescription": "Counts all demand code reads",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x3f803c0004 ",
+ "MSRValue": "0x3F803C0004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts all demand code reads that hit in the L3.",
+ "BriefDescription": "Counts all demand code reads",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "Counts writebacks (modified to exclusive) that
have any response type. Offcore response can be programmed only with a specific
pair of event select and counter MSR, and with specific event codes and
predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts writebacks (modified to exclusive) have
any response type.",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0000010008 ",
+ "MSRValue": "0x0000010008",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "Counts writebacks (modified to exclusive) that
have any response type.",
+ "BriefDescription": "Counts writebacks (modified to exclusive) have
any response type.",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "tbd Offcore response can be programmed only with
a specific pair of event select and counter MSR, and with specific event codes
and predefine mask bit value in a dedicated MSR to specify attributes of the
offcore transaction.",
+ "PublicDescription": "Counts writebacks (modified to exclusive)",
"EventCode": "0xB7, 0xBB",
- "MSRValue": "0x0080020008 ",
+ "MSRValue": "0x0080020008",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
+ "MSRIndex": "0x1a6, 0x1a7",
"SampleAfterValue": "100003",
- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NONE",
+ "BriefDescription": "Counts writebacks (modified to exclusive)",
"Offcore": "1",
"CounterHTOff": "0,1,2,3"
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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