Author: np
Date: Fri Oct 25 21:53:05 2019
New Revision: 354106
URL: https://svnweb.freebsd.org/changeset/base/354106
Log:
cxgbe(4): Use correct FetchBurstMin values for T6.
MFC after: 1 week
Sponsored by: Chelsio Communications
Modified:
head/sys/dev/cxgbe/common/t4_regs_values.h
head/sys/dev/cxgbe/iw_cxgbe/qp.c
head/sys/dev/cxgbe/t4_netmap.c
head/sys/dev/cxgbe/t4_sge.c
Modified: head/sys/dev/cxgbe/common/t4_regs_values.h
==============================================================================
--- head/sys/dev/cxgbe/common/t4_regs_values.h Fri Oct 25 21:52:02 2019
(r354105)
+++ head/sys/dev/cxgbe/common/t4_regs_values.h Fri Oct 25 21:53:05 2019
(r354106)
@@ -147,6 +147,11 @@
#define X_FETCHBURSTMIN_64B 2
#define X_FETCHBURSTMIN_128B 3
+/* T6 and later use a single-bit encoding for FetchBurstMin */
+#define X_FETCHBURSTMIN_SHIFT_T6 6
+#define X_FETCHBURSTMIN_64B_T6 0
+#define X_FETCHBURSTMIN_128B_T6 1
+
#define X_FETCHBURSTMAX_SHIFT 6
#define X_FETCHBURSTMAX_64B 0
#define X_FETCHBURSTMAX_128B 1
Modified: head/sys/dev/cxgbe/iw_cxgbe/qp.c
==============================================================================
--- head/sys/dev/cxgbe/iw_cxgbe/qp.c Fri Oct 25 21:52:02 2019
(r354105)
+++ head/sys/dev/cxgbe/iw_cxgbe/qp.c Fri Oct 25 21:53:05 2019
(r354106)
@@ -266,7 +266,8 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4
res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
V_FW_RI_RES_WR_DCAEN(0) |
V_FW_RI_RES_WR_DCACPU(0) |
- V_FW_RI_RES_WR_FBMIN(2) |
+ V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
V_FW_RI_RES_WR_FBMAX(3) |
V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
V_FW_RI_RES_WR_CIDXFTHRESH(0) |
@@ -288,7 +289,8 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4
res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
V_FW_RI_RES_WR_DCAEN(0) |
V_FW_RI_RES_WR_DCACPU(0) |
- V_FW_RI_RES_WR_FBMIN(2) |
+ V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
V_FW_RI_RES_WR_FBMAX(3) |
V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
V_FW_RI_RES_WR_CIDXFTHRESH(0) |
Modified: head/sys/dev/cxgbe/t4_netmap.c
==============================================================================
--- head/sys/dev/cxgbe/t4_netmap.c Fri Oct 25 21:52:02 2019
(r354105)
+++ head/sys/dev/cxgbe/t4_netmap.c Fri Oct 25 21:53:05 2019
(r354106)
@@ -159,7 +159,7 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq
(black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
c.fl0dcaen_to_fl0cidxfthresh =
htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
- X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
+ X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
@@ -274,9 +274,11 @@ alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq
htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) |
F_FW_EQ_ETH_CMD_FETCHRO |
V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
- c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
- V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
- V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
+ c.dcaen_to_eqsize =
+ htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
+ V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
+ V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
c.eqaddr = htobe64(nm_txq->ba);
rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
Modified: head/sys/dev/cxgbe/t4_sge.c
==============================================================================
--- head/sys/dev/cxgbe/t4_sge.c Fri Oct 25 21:52:02 2019 (r354105)
+++ head/sys/dev/cxgbe/t4_sge.c Fri Oct 25 21:53:05 2019 (r354106)
@@ -3212,7 +3212,7 @@ alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, str
}
c.fl0dcaen_to_fl0cidxfthresh =
htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
- X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
+ X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
c.fl0size = htobe16(fl->qsize);
@@ -3798,7 +3798,8 @@ ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
c.dcaen_to_eqsize =
- htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
+ htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
@@ -3842,9 +3843,11 @@ eth_eq_alloc(struct adapter *sc, struct vi_info *vi, s
htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
V_FW_EQ_ETH_CMD_IQID(eq->iqid));
- c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
- V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
- V_FW_EQ_ETH_CMD_EQSIZE(qsize));
+ c.dcaen_to_eqsize =
+ htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
+ V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
+ V_FW_EQ_ETH_CMD_EQSIZE(qsize));
c.eqaddr = htobe64(eq->ba);
rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
@@ -3886,7 +3889,8 @@ ofld_eq_alloc(struct adapter *sc, struct vi_info *vi,
V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
c.dcaen_to_eqsize =
- htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
+ htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
+ X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
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