Author: jhibbits
Date: Mon Jul 30 17:03:15 2018
New Revision: 336918
URL: https://svnweb.freebsd.org/changeset/base/336918
Log:
powerpcspe: Unconditionally save an restore SPEFSCR on task switch
The SPEFSCR is not guarded by the SPV bit in MSR, it's just another SPR.
Protect processes from other tasks setting the SPEFSCR for their own needs.
Modified:
head/sys/powerpc/powerpc/genassym.c
head/sys/powerpc/powerpc/swtch32.S
Modified: head/sys/powerpc/powerpc/genassym.c
==============================================================================
--- head/sys/powerpc/powerpc/genassym.c Mon Jul 30 16:54:51 2018
(r336917)
+++ head/sys/powerpc/powerpc/genassym.c Mon Jul 30 17:03:15 2018
(r336918)
@@ -208,6 +208,8 @@ ASSYM(PCB_CDSCR, PCB_CDSCR);
ASSYM(PCB_AIM_USR_VSID, offsetof(struct pcb, pcb_cpu.aim.usr_vsid));
ASSYM(PCB_BOOKE_DBCR0, offsetof(struct pcb, pcb_cpu.booke.dbcr0));
+ASSYM(PCB_VSCR, offsetof(struct pcb, pcb_vec.vscr));
+
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
Modified: head/sys/powerpc/powerpc/swtch32.S
==============================================================================
--- head/sys/powerpc/powerpc/swtch32.S Mon Jul 30 16:54:51 2018
(r336917)
+++ head/sys/powerpc/powerpc/swtch32.S Mon Jul 30 17:03:15 2018
(r336918)
@@ -113,6 +113,10 @@ ENTRY(cpu_switch)
bl save_vec
.L2:
+#if defined(__SPE__)
+ mfspr %r3,SPR_SPEFSCR
+ stw %r3,PCB_VSCR(%r17)
+#endif
mr %r3,%r14 /* restore old thread ptr */
bl pmap_deactivate /* Deactivate the current pmap */
@@ -163,6 +167,10 @@ blocked_loop:
bl enable_vec
.L4:
+#if defined(__SPE__)
+ lwz %r3,PCB_VSCR(%r17)
+ mtspr SPR_SPEFSCR,%r3
+#endif
/* thread to restore is in r3 */
mr %r3,%r17 /* Recover PCB ptr */
lmw %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */
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