Author: attilio
Date: Wed Dec 8 15:32:54 2010
New Revision: 216298
URL: http://svn.freebsd.org/changeset/base/216298
Log:
Use convenience macro for minimum and maximum value capping when
re-arming the watchdog timeout.
Sponsored by: Sandvine Incorporated
Submitted by: Mark Johnston <mjohnston at sandvine dot com>
Reviewed by: des
MFC after: 10 days
Modified:
head/sys/dev/ichwd/ichwd.c
head/sys/dev/ichwd/ichwd.h
Modified: head/sys/dev/ichwd/ichwd.c
==============================================================================
--- head/sys/dev/ichwd/ichwd.c Wed Dec 8 15:12:37 2010 (r216297)
+++ head/sys/dev/ichwd/ichwd.c Wed Dec 8 15:32:54 2010 (r216298)
@@ -288,30 +288,23 @@ static __inline void
ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
{
- /*
- * If the datasheets are to be believed, the minimum value
- * actually varies from chipset to chipset - 4 for ICH5 and 2 for
- * all other chipsets. I suspect this is a bug in the ICH5
- * datasheet and that the minimum is uniformly 2, but I'd rather
- * err on the side of caution.
- */
- if (timeout < 4)
- timeout = 4;
+ if (timeout < TCO_RLD_TMR_MIN)
+ timeout = TCO_RLD_TMR_MIN;
if (sc->ich_version <= 5) {
uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
- tmr_val8 &= 0xc0;
- if (timeout > 0x3f)
- timeout = 0x3f;
+ tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
+ if (timeout > TCO_RLD1_TMR_MAX)
+ timeout = TCO_RLD1_TMR_MAX;
tmr_val8 |= timeout;
ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
} else {
uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
- tmr_val16 &= 0xfc00;
- if (timeout > 0x03ff)
- timeout = 0x03ff;
+ tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
+ if (timeout > TCO_RLD2_TMR_MAX)
+ timeout = TCO_RLD2_TMR_MAX;
tmr_val16 |= timeout;
ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
}
Modified: head/sys/dev/ichwd/ichwd.h
==============================================================================
--- head/sys/dev/ichwd/ichwd.h Wed Dec 8 15:12:37 2010 (r216297)
+++ head/sys/dev/ichwd/ichwd.h Wed Dec 8 15:32:54 2010 (r216298)
@@ -199,6 +199,17 @@ struct ichwd_softc {
#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */
+/*
+ * Masks for the TCO timer value field in TCO_RLD.
+ * If the datasheets are to be believed, the minimum value actually varies
+ * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
+ * I suspect this is a bug in the ICH5 datasheet and that the minimum is
+ * uniformly 2, but I'd rather err on the side of caution.
+ */
+#define TCO_RLD_TMR_MIN 0x0004
+#define TCO_RLD1_TMR_MAX 0x003f
+#define TCO_RLD2_TMR_MAX 0x03ff
+
/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */
#define ICHWD_TICK 600000000
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