Author: adrian
Date: Thu Aug 19 16:25:15 2010
New Revision: 211510
URL: http://svn.freebsd.org/changeset/base/211510
Log:
Implement PLL generalisation in preparation for use in if_arge.
* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
definitions.
Modified:
head/sys/mips/atheros/ar71xx_chip.c
head/sys/mips/atheros/ar71xxreg.h
head/sys/mips/atheros/ar91xx_chip.c
Modified: head/sys/mips/atheros/ar71xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_chip.c Thu Aug 19 16:15:30 2010
(r211509)
+++ head/sys/mips/atheros/ar71xx_chip.c Thu Aug 19 16:25:15 2010
(r211510)
@@ -77,9 +77,6 @@ __FBSDID("$FreeBSD$");
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
-#define AR71XX_ETH0_PLL_SHIFT 17
-#define AR71XX_ETH1_PLL_SHIFT 19
-
/* XXX these shouldn't be in here - this file is a per-chip file */
/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
uint32_t u_ar71xx_cpu_freq;
@@ -143,14 +140,51 @@ ar71xx_chip_device_stopped(uint32_t mask
return ((reg & mask) == mask);
}
+/* Speed is either 10, 100 or 1000 */
static void
ar71xx_chip_set_pll_ge0(int speed)
{
+ uint32_t pll;
+
+ switch(speed) {
+ case 10:
+ pll = PLL_ETH_INT_CLK_10;
+ break;
+ case 100:
+ pll = PLL_ETH_INT_CLK_100;
+ break;
+ case 1000:
+ pll = PLL_ETH_INT_CLK_1000;
+ break;
+ default:
+ printf("ar71xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
+ return;
+ }
+
+ ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll,
AR71XX_PLL_ETH0_SHIFT);
}
static void
ar71xx_chip_set_pll_ge1(int speed)
{
+ uint32_t pll;
+
+ switch(speed) {
+ case 10:
+ pll = PLL_ETH_INT_CLK_10;
+ break;
+ case 100:
+ pll = PLL_ETH_INT_CLK_100;
+ break;
+ case 1000:
+ pll = PLL_ETH_INT_CLK_1000;
+ break;
+ default:
+ printf("ar71xx_chip_set_pll_ge1: invalid speed %d\n",
speed);
+ return;
+ }
+
+ ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll,
AR71XX_PLL_ETH1_SHIFT);
}
static void
Modified: head/sys/mips/atheros/ar71xxreg.h
==============================================================================
--- head/sys/mips/atheros/ar71xxreg.h Thu Aug 19 16:15:30 2010
(r211509)
+++ head/sys/mips/atheros/ar71xxreg.h Thu Aug 19 16:25:15 2010
(r211510)
@@ -182,6 +182,8 @@
#define PLL_BYPASS (1 << 1)
#define PLL_POWER_DOWN (1 << 0)
#define AR71XX_PLL_SEC_CONFIG 0x18050004
+#define AR71XX_PLL_ETH0_SHIFT 17
+#define AR71XX_PLL_ETH1_SHIFT 19
#define AR71XX_PLL_CPU_CLK_CTRL 0x18050008
#define AR71XX_PLL_ETH_INT0_CLK 0x18050010
#define AR71XX_PLL_ETH_INT1_CLK 0x18050014
@@ -501,4 +503,27 @@ ar71xx_ddr_flush(uint32_t reg)
;
}
+static inline void
+ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t
pll_reg_shift)
+{
+ uint32_t sec_cfg;
+
+ /* set PLL registers */
+ sec_cfg = ATH_READ_REG(cfg_reg);
+ sec_cfg &= ~(3 << pll_reg_shift);
+ sec_cfg |= (2 << pll_reg_shift);
+
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+
+ ATH_WRITE_REG(pll_reg, pll);
+ sec_cfg |= (3 << pll_reg_shift);
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+
+ sec_cfg &= ~(3 << pll_reg_shift);
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+}
+
#endif /* _AR71XX_REG_H_ */
Modified: head/sys/mips/atheros/ar91xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar91xx_chip.c Thu Aug 19 16:15:30 2010
(r211509)
+++ head/sys/mips/atheros/ar91xx_chip.c Thu Aug 19 16:25:15 2010
(r211510)
@@ -117,11 +117,45 @@ ar91xx_chip_device_stopped(uint32_t mask
static void
ar91xx_chip_set_pll_ge0(int speed)
{
+ uint32_t pll;
+
+ switch(speed) {
+ case 10:
+ pll = AR91XX_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR91XX_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
+ return;
+ }
+ ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT);
}
static void
ar91xx_chip_set_pll_ge1(int speed)
{
+ uint32_t pll;
+
+ switch(speed) {
+ case 10:
+ pll = AR91XX_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR91XX_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
speed);
+ return;
+ }
+ ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
}
static void
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