Author: marius
Date: Wed Mar 17 20:23:14 2010
New Revision: 205258
URL: http://svn.freebsd.org/changeset/base/205258
Log:
- Add TTE and context register bits for the additional page sizes supported
by UltraSparc-IV and -IV+ as well as SPARC64 V, VI, VII and VIIIfx CPUs.
- Replace TLB_PCXR_PGSZ_MASK and TLB_SCXR_PGSZ_MASK with TLB_CXR_PGSZ_MASK
which just is the complement of TLB_CXR_CTX_MASK instead of trying to
assemble it from the page size bits which vary across CPUs.
- Add macros for the remainder of the SFSR bits, which are useful for at
least debugging purposes.
Modified:
head/sys/sparc64/include/tlb.h
head/sys/sparc64/include/tte.h
head/sys/sparc64/sparc64/genassym.c
head/sys/sparc64/sparc64/pmap.c
head/sys/sparc64/sparc64/swtch.S
Modified: head/sys/sparc64/include/tlb.h
==============================================================================
--- head/sys/sparc64/include/tlb.h Wed Mar 17 20:17:25 2010
(r205257)
+++ head/sys/sparc64/include/tlb.h Wed Mar 17 20:23:14 2010
(r205258)
@@ -1,5 +1,6 @@
/*-
* Copyright (c) 2001 Jake Burkholder.
+ * Copyright (c) 2008, 2010 Marius Strobl <mar...@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,11 +36,11 @@
#define TLB_DIRECT_ADDRESS_MASK ((1UL <<
TLB_DIRECT_ADDRESS_BITS) - 1)
#define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS)
- 1)
-#define TLB_PHYS_TO_DIRECT(pa) \
+#define TLB_PHYS_TO_DIRECT(pa)
\
((pa) | VM_MIN_DIRECT_ADDRESS)
-#define TLB_DIRECT_TO_PHYS(va) \
+#define TLB_DIRECT_TO_PHYS(va)
\
((va) & TLB_DIRECT_ADDRESS_MASK)
-#define TLB_DIRECT_TO_TTE_MASK \
+#define TLB_DIRECT_TO_TTE_MASK
\
(TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
#define TLB_DAR_SLOT_SHIFT (3)
@@ -56,18 +57,21 @@
(((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
#define TLB_CXR_CTX_SHIFT (0)
#define TLB_CXR_PGSZ_BITS (3)
-#define TLB_PCXR_PGSZ_MASK
\
- ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ0_SHIFT) | \
- (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ1_SHIFT) | \
- (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ0_SHIFT) | \
- (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ1_SHIFT))
+#define TLB_CXR_PGSZ_MASK (~TLB_CXR_CTX_MASK)
+#define TLB_PCXR_N_IPGSZ0_SHIFT (53) /* SPARC64 VI, VII,
VIIIfx */
+#define TLB_PCXR_N_IPGSZ1_SHIFT (50) /* SPARC64 VI, VII,
VIIIfx */
#define TLB_PCXR_N_PGSZ0_SHIFT (61)
#define TLB_PCXR_N_PGSZ1_SHIFT (58)
+#define TLB_PCXR_N_PGSZ_I_SHIFT (55) /* US-IV+ */
+#define TLB_PCXR_P_IPGSZ0_SHIFT (24) /* SPARC64 VI, VII,
VIIIfx */
+#define TLB_PCXR_P_IPGSZ1_SHIFT (27) /* SPARC64 VI, VII,
VIIIfx */
#define TLB_PCXR_P_PGSZ0_SHIFT (16)
#define TLB_PCXR_P_PGSZ1_SHIFT (19)
-#define TLB_SCXR_PGSZ_MASK
\
- ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ0_SHIFT) | \
- (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ1_SHIFT))
+/*
+ * Note that the US-IV+ documentation appears to have TLB_PCXR_P_PGSZ_I_SHIFT
+ * and TLB_PCXR_P_PGSZ0_SHIFT erroneously inverted.
+ */
+#define TLB_PCXR_P_PGSZ_I_SHIFT (22) /* US-IV+ */
#define TLB_SCXR_S_PGSZ1_SHIFT (19)
#define TLB_SCXR_S_PGSZ0_SHIFT (16)
@@ -87,7 +91,7 @@
#define TLB_DEMAP_TYPE_SHIFT (6)
#define TLB_DEMAP_TYPE_PAGE (0)
#define TLB_DEMAP_TYPE_CONTEXT (1)
-#define TLB_DEMAP_TYPE_ALL (2) /* USIII and beyond
only */
+#define TLB_DEMAP_TYPE_ALL (2) /* US-III and beyond
only */
#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK)
#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT)
@@ -118,9 +122,17 @@
#define MMU_SFSR_FT_SIZE (6)
#define MMU_SFSR_CT_SIZE (2)
-#define MMU_SFSR_GET_ASI(sfsr) \
+#define MMU_SFSR_GET_ASI(sfsr)
\
(((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
+#define MMU_SFSR_GET_FT(sfsr)
\
+ (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1))
+#define MMU_SFSR_GET_CT(sfsr)
\
+ (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1))
+
+#define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT)
+#define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIFT)
#define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT)
+#define MMU_SFSR_OW (1UL << MMU_SFSR_OW_SHIFT)
#define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT)
typedef void tlb_flush_nonlocked_t(void);
Modified: head/sys/sparc64/include/tte.h
==============================================================================
--- head/sys/sparc64/include/tte.h Wed Mar 17 20:17:25 2010
(r205257)
+++ head/sys/sparc64/include/tte.h Wed Mar 17 20:23:14 2010
(r205258)
@@ -36,25 +36,42 @@
#define TD_SIZE_SHIFT (61)
#define TD_SOFT2_SHIFT (50)
+#define TD_RSVD2_SHIFT (49)
+#define TD_SIZE2_SHIFT (48)
#define TD_DIAG_SF_SHIFT (41)
#define TD_RSVD_CH_SHIFT (43)
+#define TD_RSVD_OC_SHIFT (47)
+#define TD_RSVD_PT_SHIFT TD_RSVD_CH_SHIFT
+#define TD_RSVD_VE_SHIFT (41)
#define TD_PA_SHIFT (13)
#define TD_SOFT_SHIFT (7)
#define TD_SIZE_BITS (2)
#define TD_SOFT2_BITS (9)
-#define TD_DIAG_SF_BITS (9)
-#define TD_RSVD_CH_BITS (7)
-#define TD_PA_CH_BITS (30)
-#define TD_PA_SF_BITS (28)
+#define TD_RSVD2_BITS (1) /* US-IV+, SPARC64 VI, VII, VIIIfx */
+#define TD_SIZE2_BITS (1) /* US-IV+, SPARC64 VI, VII, VIIIfx */
+#define TD_DIAG_SF_BITS (9) /* US-I, II{,e,i} */
+#define TD_RSVD_CH_BITS (7) /* US-III{,i,+}, US-IV, SPARC64 V */
+#define TD_RSVD_OC_BITS (1) /* SPARC64 VI, VII */
+#define TD_RSVD_PT_BITS (5) /* US-IV+, SPARC64 VI, VII */
+#define TD_RSVD_VE_BITS (7) /* SPARC64 VIIIfx */
+#define TD_PA_CH_BITS (30) /* US-III{,i,+}, US-IV{,+}, SPARC64 V */
+#define TD_PA_OC_BITS (34) /* SPARC64 VI, VII */
+#define TD_PA_SF_BITS (28) /* US-I, II{,e,i}, SPARC64 VIIIfx */
#define TD_PA_BITS TD_PA_CH_BITS
#define TD_SOFT_BITS (6)
#define TD_SIZE_MASK ((1UL << TD_SIZE_BITS) - 1)
#define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
+#define TD_RSVD2_MASK ((1UL << TD_RSVD2_BITS) - 1)
+#define TD_SIZE2_MASK ((1UL << TD_SIZE2_BITS) - 1)
#define TD_DIAG_SF_MASK ((1UL << TD_DIAG_SF_BITS) - 1)
#define TD_RSVD_CH_MASK ((1UL << TD_RSVD_CH_BITS) - 1)
+#define TD_RSVD_OC_MASK ((1UL << TD_RSVD_OC_BITS) - 1)
+#define TD_RSVD_PT_MASK ((1UL << TD_RSVD_PT_BITS) - 1)
+#define TD_RSVD_VE_MASK ((1UL << TD_RSVD_VE_BITS) - 1)
#define TD_PA_CH_MASK ((1UL << TD_PA_CH_BITS) - 1)
+#define TD_PA_OC_MASK ((1UL << TD_PA_OC_BITS) - 1)
#define TD_PA_SF_MASK ((1UL << TD_PA_SF_BITS) - 1)
#define TD_PA_MASK ((1UL << TD_PA_BITS) - 1)
#define TD_SOFT_MASK ((1UL << TD_SOFT_BITS) - 1)
@@ -63,6 +80,9 @@
#define TS_64K (1UL)
#define TS_512K (2UL)
#define TS_4M (3UL)
+#define TS_32M (4UL) /* US-IV+, SPARC64 VI, VII only */
+#define TS_256M (5UL) /* US-IV+, SPARC64 VI, VII only */
+#define TS_2G (6UL) /* SPARC64 VIIIfx only */
#define TS_MIN TS_8K
#define TS_MAX TS_4M
@@ -72,6 +92,15 @@
#define TD_64K (TS_64K << TD_SIZE_SHIFT)
#define TD_512K (TS_512K << TD_SIZE_SHIFT)
#define TD_4M (TS_4M << TD_SIZE_SHIFT)
+#define TD_32M
\
+ (((TS_32M & TD_SIZE_MASK) << TD_SIZE_SHIFT) | \
+ (TD_SIZE2_MASK << TD_SIZE2_SHIFT))
+#define TD_256M
\
+ (((TS_256M & TD_SIZE_MASK) << TD_SIZE_SHIFT) | \
+ (TD_SIZE2_MASK << TD_SIZE2_SHIFT))
+#define TD_2G
\
+ (((TS_2G & TD_SIZE_MASK) << TD_SIZE_SHIFT) | \
+ (TD_SIZE2_MASK << TD_SIZE2_SHIFT))
#define TD_NFO (1UL << 60)
#define TD_IE (1UL << 59)
#define TD_PA(pa) ((pa) & (TD_PA_MASK << TD_PA_SHIFT))
@@ -94,29 +123,28 @@
#define TV_VPN(va, sz) ((((va) >> TTE_PAGE_SHIFT(sz)) << TV_SIZE_BITS)
| sz)
#define TTE_SIZE_SPREAD (3)
-#define TTE_PAGE_SHIFT(sz) \
+#define TTE_PAGE_SHIFT(sz)
\
(PAGE_SHIFT + ((sz) * TTE_SIZE_SPREAD))
-#define TTE_GET_SIZE(tp) \
+#define TTE_GET_SIZE(tp)
\
(((tp)->tte_data >> TD_SIZE_SHIFT) & TD_SIZE_MASK)
-#define TTE_GET_PAGE_SHIFT(tp) \
+#define TTE_GET_PAGE_SHIFT(tp)
\
TTE_PAGE_SHIFT(TTE_GET_SIZE(tp))
-#define TTE_GET_PAGE_SIZE(tp) \
+#define TTE_GET_PAGE_SIZE(tp)
\
(1 << TTE_GET_PAGE_SHIFT(tp))
-#define TTE_GET_PAGE_MASK(tp) \
+#define TTE_GET_PAGE_MASK(tp)
\
(TTE_GET_PAGE_SIZE(tp) - 1)
-#define TTE_GET_PA(tp) \
+#define TTE_GET_PA(tp)
\
((tp)->tte_data & (TD_PA_MASK << TD_PA_SHIFT))
-#define TTE_GET_VPN(tp) \
+#define TTE_GET_VPN(tp)
\
((tp)->tte_vpn >> TV_SIZE_BITS)
-#define TTE_GET_VA(tp) \
+#define TTE_GET_VA(tp)
\
(TTE_GET_VPN(tp) << TTE_GET_PAGE_SHIFT(tp))
-#define TTE_GET_PMAP(tp) \
- (((tp)->tte_data & TD_P) != 0 ? \
- (kernel_pmap) : \
- (PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)(tp)))->md.pmap))
-#define TTE_ZERO(tp) \
+#define TTE_GET_PMAP(tp)
\
+ (((tp)->tte_data & TD_P) != 0 ? (kernel_pmap) : \
+ (PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)(tp)))->md.pmap))
+#define TTE_ZERO(tp)
\
memset(tp, 0, sizeof(*tp))
struct pmap;
@@ -130,6 +158,7 @@ struct tte {
static __inline int
tte_match(struct tte *tp, vm_offset_t va)
{
+
return (((tp->tte_data & TD_V) != 0) &&
(tp->tte_vpn == TV_VPN(va, TTE_GET_SIZE(tp))));
}
Modified: head/sys/sparc64/sparc64/genassym.c
==============================================================================
--- head/sys/sparc64/sparc64/genassym.c Wed Mar 17 20:17:25 2010
(r205257)
+++ head/sys/sparc64/sparc64/genassym.c Wed Mar 17 20:23:14 2010
(r205258)
@@ -139,7 +139,7 @@ ASSYM(TD_W, TD_W);
ASSYM(TS_MIN, TS_MIN);
ASSYM(TS_MAX, TS_MAX);
ASSYM(TLB_DAR_SLOT_SHIFT, TLB_DAR_SLOT_SHIFT);
-ASSYM(TLB_PCXR_PGSZ_MASK, TLB_PCXR_PGSZ_MASK);
+ASSYM(TLB_CXR_PGSZ_MASK, TLB_CXR_PGSZ_MASK);
ASSYM(TLB_DIRECT_TO_TTE_MASK, TLB_DIRECT_TO_TTE_MASK);
ASSYM(TV_SIZE_BITS, TV_SIZE_BITS);
#endif
Modified: head/sys/sparc64/sparc64/pmap.c
==============================================================================
--- head/sys/sparc64/sparc64/pmap.c Wed Mar 17 20:17:25 2010
(r205257)
+++ head/sys/sparc64/sparc64/pmap.c Wed Mar 17 20:23:14 2010
(r205258)
@@ -572,7 +572,7 @@ pmap_map_tsb(void)
* FP block operations in the kernel).
*/
stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
- TLB_SCXR_PGSZ_MASK) | TLB_CTX_KERNEL);
+ TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
flush(KERNBASE);
intr_restore(s);
@@ -1989,7 +1989,7 @@ pmap_activate(struct thread *td)
stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
- TLB_PCXR_PGSZ_MASK) | context);
+ TLB_CXR_PGSZ_MASK) | context);
flush(KERNBASE);
mtx_unlock_spin(&sched_lock);
Modified: head/sys/sparc64/sparc64/swtch.S
==============================================================================
--- head/sys/sparc64/sparc64/swtch.S Wed Mar 17 20:17:25 2010
(r205257)
+++ head/sys/sparc64/sparc64/swtch.S Wed Mar 17 20:23:14 2010
(r205258)
@@ -237,7 +237,7 @@ ENTRY(cpu_switch)
stxa %i4, [%i5] ASI_DMMU
mov AA_IMMU_TSB, %i5
stxa %i4, [%i5] ASI_IMMU
- setx TLB_PCXR_PGSZ_MASK, %i5, %i4
+ setx TLB_CXR_PGSZ_MASK, %i5, %i4
mov AA_DMMU_PCXR, %i5
ldxa [%i5] ASI_DMMU, %l1
and %l1, %i4, %l1
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