Author: nwhitehorn
Date: Mon Mar 15 00:27:40 2010
New Revision: 205163
URL: http://svn.freebsd.org/changeset/base/205163
Log:
Fix two small bugs. The PowerPC 970 does not support non-coherent memory
access, and reflects this by autonomously writing LPTE_M into PTE entries.
As such, we should not panic if LPTE_M changes by itself. While here,
fix a harmless typo in moea64_sync_icache().
Modified:
head/sys/powerpc/aim/mmu_oea64.c
Modified: head/sys/powerpc/aim/mmu_oea64.c
==============================================================================
--- head/sys/powerpc/aim/mmu_oea64.c Sun Mar 14 23:52:30 2010
(r205162)
+++ head/sys/powerpc/aim/mmu_oea64.c Mon Mar 15 00:27:40 2010
(r205163)
@@ -2268,7 +2268,7 @@ moea64_pvo_to_pte(const struct pvo_entry
}
if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) &
- ~(LPTE_CHG|LPTE_REF)) != 0) {
+ ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) {
panic("moea64_pvo_to_pte: pvo %p pte does not match "
"pte %p in moea64_pteg_table difference is %#x",
pvo, pt,
@@ -2511,7 +2511,7 @@ moea64_sync_icache(mmu_t mmu, pmap_t pm,
len = MIN(lim - va, sz);
pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
if (pvo != NULL) {
- pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
+ pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) |
(va & ADDR_POFF);
moea64_syncicache(pm, va, pa, len);
}
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