Author: markj
Date: Thu Feb 27 01:04:35 2014
New Revision: 262542
URL: http://svnweb.freebsd.org/changeset/base/262542
Log:
Move some files that are identical on i386 and amd64 to an x86 subdirectory
rather than keeping duplicate copies.
Discussed with: avg
MFC after: 1 week
Added:
head/sys/cddl/dev/dtrace/x86/
head/sys/cddl/dev/dtrace/x86/dis_tables.c
- copied unchanged from r262521,
head/sys/cddl/dev/dtrace/amd64/dis_tables.c
head/sys/cddl/dev/dtrace/x86/dis_tables.h
- copied unchanged from r262521,
head/sys/cddl/dev/dtrace/amd64/dis_tables.h
head/sys/cddl/dev/dtrace/x86/regset.h
- copied unchanged from r262521, head/sys/cddl/dev/dtrace/amd64/regset.h
Deleted:
head/sys/cddl/dev/dtrace/amd64/dis_tables.c
head/sys/cddl/dev/dtrace/amd64/dis_tables.h
head/sys/cddl/dev/dtrace/amd64/regset.h
head/sys/cddl/dev/dtrace/i386/dis_tables.c
head/sys/cddl/dev/dtrace/i386/dis_tables.h
head/sys/cddl/dev/dtrace/i386/regset.h
Modified:
head/cddl/lib/libdtrace/Makefile
head/sys/cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c
head/sys/modules/dtrace/dtrace/Makefile
Modified: head/cddl/lib/libdtrace/Makefile
==============================================================================
--- head/cddl/lib/libdtrace/Makefile Thu Feb 27 01:01:02 2014
(r262541)
+++ head/cddl/lib/libdtrace/Makefile Thu Feb 27 01:04:35 2014
(r262542)
@@ -69,9 +69,11 @@ CFLAGS+= -I${.OBJDIR} -I${.CURDIR} \
#CFLAGS+= -DYYDEBUG
.if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64"
+CFLAGS+= -I${.CURDIR}/../../../sys/cddl/dev/dtrace/x86
CFLAGS+= -I${OPENSOLARIS_SYS_DISTDIR}/uts/intel -DDIS_MEM
.PATH: ${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libdtrace/i386
.PATH: ${.CURDIR}/../../../sys/cddl/dev/dtrace/${MACHINE_ARCH}
+.PATH: ${.CURDIR}/../../../sys/cddl/dev/dtrace/x86
.elif ${MACHINE_CPUARCH} == "sparc64"
CFLAGS+= -I${OPENSOLARIS_SYS_DISTDIR}/uts/sparc
.PATH: ${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libdtrace/sparc
Modified: head/sys/cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c
==============================================================================
--- head/sys/cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c Thu Feb
27 01:01:02 2014 (r262541)
+++ head/sys/cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c Thu Feb
27 01:04:35 2014 (r262542)
@@ -47,7 +47,7 @@
#include <sys/types.h>
#include <sys/proc.h>
#include <sys/dtrace_bsd.h>
-#include <cddl/dev/dtrace/i386/regset.h>
+#include <cddl/dev/dtrace/x86/regset.h>
#include <machine/segments.h>
#include <machine/reg.h>
#include <machine/pcb.h>
Copied: head/sys/cddl/dev/dtrace/x86/dis_tables.c (from r262521,
head/sys/cddl/dev/dtrace/amd64/dis_tables.c)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/cddl/dev/dtrace/x86/dis_tables.c Thu Feb 27 01:04:35 2014
(r262542, copy of r262521, head/sys/cddl/dev/dtrace/amd64/dis_tables.c)
@@ -0,0 +1,4841 @@
+/*
+ *
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+/*
+ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
+ */
+
+/*
+ * Copyright (c) 2010, Intel Corporation.
+ * All rights reserved.
+ */
+
+/* Copyright (c) 1988 AT&T */
+/* All Rights Reserved */
+
+/*
+ * $FreeBSD$
+ */
+
+#include "dis_tables.h"
+
+/* BEGIN CSTYLED */
+
+/*
+ * Disassembly begins in dis_distable, which is equivalent to the One-byte
+ * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
+ * decoding loops then traverse out through the other tables as necessary to
+ * decode a given instruction.
+ *
+ * The behavior of this file can be controlled by one of the following flags:
+ *
+ * DIS_TEXT Include text for disassembly
+ * DIS_MEM Include memory-size calculations
+ *
+ * Either or both of these can be defined.
+ *
+ * This file is not, and will never be, cstyled. If anything, the tables
should
+ * be taken out another tab stop or two so nothing overlaps.
+ */
+
+/*
+ * These functions must be provided for the consumer to do disassembly.
+ */
+#ifdef DIS_TEXT
+extern char *strncpy(char *, const char *, size_t);
+extern size_t strlen(const char *);
+extern int strcmp(const char *, const char *);
+extern int strncmp(const char *, const char *, size_t);
+extern size_t strlcat(char *, const char *, size_t);
+#endif
+
+
+#define TERM 0 /* used to indicate that the 'indirect'
*/
+ /* field terminates - no pointer. */
+
+/* Used to decode instructions. */
+typedef struct instable {
+ struct instable *it_indirect; /* for decode op codes */
+ uchar_t it_adrmode;
+#ifdef DIS_TEXT
+ char it_name[NCPS];
+ uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
+#endif
+#ifdef DIS_MEM
+ uint_t it_size:16;
+#endif
+ uint_t it_invalid64:1; /* opcode invalid in amd64 */
+ uint_t it_always64:1; /* 64 bit when in 64 bit mode */
+ uint_t it_invalid32:1; /* invalid in IA32 */
+ uint_t it_stackop:1; /* push/pop stack operation */
+} instable_t;
+
+/*
+ * Instruction formats.
+ */
+enum {
+ UNKNOWN,
+ MRw,
+ IMlw,
+ IMw,
+ IR,
+ OA,
+ AO,
+ MS,
+ SM,
+ Mv,
+ Mw,
+ M, /* register or memory */
+ Mb, /* register or memory, always byte sized */
+ MO, /* memory only (no registers) */
+ PREF,
+ SWAPGS,
+ MONITOR_MWAIT,
+ R,
+ RA,
+ SEG,
+ MR,
+ RM,
+ IA,
+ MA,
+ SD,
+ AD,
+ SA,
+ D,
+ INM,
+ SO,
+ BD,
+ I,
+ P,
+ V,
+ DSHIFT, /* for double shift that has an 8-bit immediate */
+ U,
+ OVERRIDE,
+ NORM, /* instructions w/o ModR/M byte, no memory access */
+ IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
+ O, /* for call */
+ JTAB, /* jump table */
+ IMUL, /* for 186 iimul instr */
+ CBW, /* so data16 can be evaluated for cbw and variants */
+ MvI, /* for 186 logicals */
+ ENTER, /* for 186 enter instr */
+ RMw, /* for 286 arpl instr */
+ Ib, /* for push immediate byte */
+ F, /* for 287 instructions */
+ FF, /* for 287 instructions */
+ FFC, /* for 287 instructions */
+ DM, /* 16-bit data */
+ AM, /* 16-bit addr */
+ LSEG, /* for 3-bit seg reg encoding */
+ MIb, /* for 386 logicals */
+ SREG, /* for 386 special registers */
+ PREFIX, /* a REP instruction prefix */
+ LOCK, /* a LOCK instruction prefix */
+ INT3, /* The int 3 instruction, which has a fake operand */
+ INTx, /* The normal int instruction, with explicit int num */
+ DSHIFTcl, /* for double shift that implicitly uses %cl */
+ CWD, /* so data16 can be evaluated for cwd and variants */
+ RET, /* single immediate 16-bit operand */
+ MOVZ, /* for movs and movz, with different size operands */
+ CRC32, /* for crc32, with different size operands */
+ XADDB, /* for xaddb */
+ MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
+ MOVBE, /* movbe instruction */
+
+/*
+ * MMX/SIMD addressing modes.
+ */
+
+ MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
+ MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
+ MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
+ MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
+ MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
+ MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
+ MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
+ MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
+ MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
+ MMOSH, /* Prefixable MMX mm,imm8 */
+ MM, /* MMX/SIMD-Int mm/mem -> mm */
+ MMS, /* MMX/SIMD-Int mm -> mm/mem */
+ MMSH, /* MMX mm,imm8 */
+ XMMO, /* Prefixable SIMD xmm/mem -> xmm */
+ XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
+ XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
+ XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
+ XMMOX3, /* Prefixable SIMD xmm -> r32 */
+ XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
+ XMMOM, /* Prefixable SIMD xmm -> mem */
+ XMMOMS, /* Prefixable SIMD mem -> xmm */
+ XMM, /* SIMD xmm/mem -> xmm */
+ XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
+ XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
+ XMMXIMPL, /* SIMD xmm -> xmm (mem) */
+ XMM3P, /* SIMD xmm -> r32,imm8 */
+ XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8
*/
+ XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
+ XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
+ XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
+ XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
+ XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
+ XMMS, /* SIMD xmm -> xmm/mem */
+ XMMM, /* SIMD mem -> xmm */
+ XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
+ XMMMS, /* SIMD xmm -> mem */
+ XMM3MX, /* SIMD r32/mem -> xmm */
+ XMM3MXS, /* SIMD xmm -> r32/mem */
+ XMMSH, /* SIMD xmm,imm8 */
+ XMMXM3, /* SIMD xmm/mem -> r32 */
+ XMMX3, /* SIMD xmm -> r32 */
+ XMMXMM, /* SIMD xmm/mem -> mm */
+ XMMMX, /* SIMD mm -> xmm */
+ XMMXM, /* SIMD xmm -> mm */
+ XMMX2I, /* SIMD xmm -> xmm,
imm, imm */
+ XMM2I, /* SIMD xmm, imm, imm */
+ XMMFENCE, /* SIMD lfence or mfence */
+ XMMSFNC, /* SIMD sfence (none or mem) */
+ XGETBV_XSETBV,
+ VEX_NONE, /* VEX no operand */
+ VEX_MO, /* VEX mod_rm -> implicit reg
*/
+ VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
+ VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
+ VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
+ VEX_MX, /* VEX mod_rm -> mod_reg */
+ VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
+ VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
+ VEX_MR, /* VEX mod_rm -> mod_reg */
+ VEX_RRI, /* VEX mod_reg, mod_rm ->
implicit(eflags/r32) */
+ VEX_RX, /* VEX mod_reg -> mod_rm */
+ VEX_RR, /* VEX mod_rm -> mod_reg */
+ VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
+ VEX_RM, /* VEX mod_reg -> mod_rm */
+ VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
+ VEX_RMX /* VEX VEX.vvvv, mod_rm -> mod_reg */
+};
+
+/*
+ * VEX prefixes
+ */
+#define VEX_2bytes 0xC5 /* the first byte of two-byte form */
+#define VEX_3bytes 0xC4 /* the first byte of three-byte form */
+
+#define FILL 0x90 /* Fill byte used for alignment (nop) */
+
+/*
+** Register numbers for the i386
+*/
+#define EAX_REGNO 0
+#define ECX_REGNO 1
+#define EDX_REGNO 2
+#define EBX_REGNO 3
+#define ESP_REGNO 4
+#define EBP_REGNO 5
+#define ESI_REGNO 6
+#define EDI_REGNO 7
+
+/*
+ * modes for immediate values
+ */
+#define MODE_NONE 0
+#define MODE_IPREL 1 /* signed IP relative value */
+#define MODE_SIGNED 2 /* sign extended immediate */
+#define MODE_IMPLIED 3 /* constant value implied from opcode */
+#define MODE_OFFSET 4 /* offset part of an address */
+#define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
+
+/*
+ * The letters used in these macros are:
+ * IND - indirect to another to another table
+ * "T" - means to Terminate indirections (this is the final opcode)
+ * "S" - means "operand length suffix required"
+ * "NS" - means "no suffix" which is the operand length suffix of the opcode
+ * "Z" - means instruction size arg required
+ * "u" - means the opcode is invalid in IA32 but valid in amd64
+ * "x" - means the opcode is invalid in amd64, but not IA32
+ * "y" - means the operand size is always 64 bits in 64 bit mode
+ * "p" - means push/pop stack operation
+ */
+
+#if defined(DIS_TEXT) && defined(DIS_MEM)
+#define IND(table) {(instable_t *)table, 0, "", 0, 0, 0,
0, 0, 0}
+#define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1,
0, 0, 0}
+#define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
+#define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
+#define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
+#define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
+#define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
+#define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
+#define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
+#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
+#define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
+#define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
+#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
+#define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
+#define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
+#define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
+#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
+#elif defined(DIS_TEXT)
+#define IND(table) {(instable_t *)table, 0, "", 0, 0, 0,
0, 0}
+#define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0,
0, 0}
+#define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
+#define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
+#define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
+#define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
+#define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
+#define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
+#define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
+#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
+#define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
+#define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
+#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
+#define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
+#define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
+#define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
+#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
+#elif defined(DIS_MEM)
+#define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
+#define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
+#define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
+#define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
+#define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
+#define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
+#define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
+#define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
+#define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
+#define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
+#define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
+#define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
+#define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
+#define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
+#define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
+#define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
+#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
+#else
+#define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
+#define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
+#define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
+#define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
+#define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
+#define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
+#define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
+#define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
+#define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
+#define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
+#define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
+#define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
+#define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
+#define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
+#define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
+#define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
+#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
+#endif
+
+#ifdef DIS_TEXT
+/*
+ * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
+ */
+const char *const dis_addr16[3][8] = {
+"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
+ "(%bx)",
+"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
+ "(%bx)",
+"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
+ "(%bx)",
+};
+
+
+/*
+ * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
+ */
+const char *const dis_addr32_mode0[16] = {
+ "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
+ "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
+};
+
+const char *const dis_addr32_mode12[16] = {
+ "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
+ "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
+};
+
+/*
+ * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
+ */
+const char *const dis_addr64_mode0[16] = {
+ "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)",
"(%rdi)",
+ "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
+};
+const char *const dis_addr64_mode12[16] = {
+ "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)",
"(%rdi)",
+ "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
+};
+
+/*
+ * decode for scale from SIB byte
+ */
+const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
+
+/*
+ * register decoding for normal references to registers (ie. not addressing)
+ */
+const char *const dis_REG8[16] = {
+ "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
+ "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
+};
+
+const char *const dis_REG8_REX[16] = {
+ "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
+ "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
+};
+
+const char *const dis_REG16[16] = {
+ "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
+ "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
+};
+
+const char *const dis_REG32[16] = {
+ "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
+ "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
+};
+
+const char *const dis_REG64[16] = {
+ "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
+};
+
+const char *const dis_DEBUGREG[16] = {
+ "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
+ "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
+};
+
+const char *const dis_CONTROLREG[16] = {
+ "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
+ "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
+};
+
+const char *const dis_TESTREG[16] = {
+ "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
+ "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
+};
+
+const char *const dis_MMREG[16] = {
+ "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
+ "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
+};
+
+const char *const dis_XMMREG[16] = {
+ "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
+ "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14",
"%xmm15"
+};
+
+const char *const dis_YMMREG[16] = {
+ "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
+ "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14",
"%ymm15"
+};
+
+const char *const dis_SEGREG[16] = {
+ "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
+ "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
+};
+
+/*
+ * SIMD predicate suffixes
+ */
+const char *const dis_PREDSUFFIX[8] = {
+ "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
+};
+
+const char *const dis_AVXvgrp7[3][8] = {
+ /*0 1 2 3 4 5
6 7*/
+/*71*/ {"", "", "vpsrlw", "", "vpsraw", "",
"vpsllw", ""},
+/*72*/ {"", "", "vpsrld", "", "vpsrad", "",
"vpslld", ""},
+/*73*/ {"", "", "vpsrlq", "vpsrldq", "", "",
"vpsllq", "vpslldq"}
+};
+
+#endif /* DIS_TEXT */
+
+/*
+ * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
+ */
+const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
+
+/*
+ * "decode table" for pause and clflush instructions
+ */
+const instable_t dis_opPause = TNS("pause", NORM);
+
+/*
+ * Decode table for 0x0F00 opcodes
+ */
+const instable_t dis_op0F00[8] = {
+
+/* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M),
TNSy("ltr",M),
+/* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID,
INVALID,
+};
+
+
+/*
+ * Decode table for 0x0F01 opcodes
+ */
+const instable_t dis_op0F01[8] = {
+
+/* [0] */ TNSZ("sgdt",MO,6), TNSZ("sidt",MONITOR_MWAIT,6),
TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",MO,6),
+/* [4] */ TNSZ("smsw",M,2), INVALID,
TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS),
+};
+
+/*
+ * Decode table for 0x0F18 opcodes -- SIMD prefetch
+ */
+const instable_t dis_op0F18[8] = {
+
+/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF),
TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
+/* [4] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+/*
+ * Decode table for 0x0FAE opcodes -- SIMD state save/restore
+ */
+const instable_t dis_op0FAE[8] = {
+/* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512),
TNS("ldmxcsr",M), TNS("stmxcsr",M),
+/* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE),
TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
+};
+
+/*
+ * Decode table for 0x0FBA opcodes
+ */
+
+const instable_t dis_op0FBA[8] = {
+
+/* [0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb),
TS("btc",MIb),
+};
+
+/*
+ * Decode table for 0x0FC7 opcode
+ */
+
+const instable_t dis_op0FC7[8] = {
+
+/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID,
INVALID,
+/* [4] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+
+/*
+ * Decode table for 0x0FC8 opcode -- 486 bswap instruction
+ *
+ *bit pattern: 0000 1111 1100 1reg
+ */
+const instable_t dis_op0FC8[4] = {
+/* [0] */ TNS("bswap",R), INVALID, INVALID,
INVALID,
+};
+
+/*
+ * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
+ */
+const instable_t dis_op0F7123[4][8] = {
+{
+/* [70].0 */ INVALID, INVALID, INVALID,
INVALID,
+/* .4 */ INVALID, INVALID, INVALID,
INVALID,
+}, {
+/* [71].0 */ INVALID, INVALID,
TNS("psrlw",MMOSH), INVALID,
+/* .4 */ TNS("psraw",MMOSH), INVALID,
TNS("psllw",MMOSH), INVALID,
+}, {
+/* [72].0 */ INVALID, INVALID,
TNS("psrld",MMOSH), INVALID,
+/* .4 */ TNS("psrad",MMOSH), INVALID,
TNS("pslld",MMOSH), INVALID,
+}, {
+/* [73].0 */ INVALID, INVALID,
TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
+/* .4 */ INVALID, INVALID,
TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
+} };
+
+/*
+ * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
+ */
+const instable_t dis_opSIMD7123[32] = {
+/* [70].0 */ INVALID, INVALID, INVALID,
INVALID,
+/* .4 */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [71].0 */ INVALID, INVALID,
TNS("psrlw",XMMSH), INVALID,
+/* .4 */ TNS("psraw",XMMSH), INVALID,
TNS("psllw",XMMSH), INVALID,
+
+/* [72].0 */ INVALID, INVALID,
TNS("psrld",XMMSH), INVALID,
+/* .4 */ TNS("psrad",XMMSH), INVALID,
TNS("pslld",XMMSH), INVALID,
+
+/* [73].0 */ INVALID, INVALID,
TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
+/* .4 */ INVALID, INVALID,
TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
+};
+
+/*
+ * SIMD instructions have been wedged into the existing IA32 instruction
+ * set through the use of prefixes. That is, while 0xf0 0x58 may be
+ * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
+ * instruction - addss. At present, three prefixes have been coopted in
+ * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
+ * following tables are used to provide the prefixed instruction names.
+ * The arrays are sparse, but they're fast.
+ */
+
+/*
+ * Decode table for SIMD instructions with the address size (0x66) prefix.
+ */
+const instable_t dis_opSIMDdata16[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16),
TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
+/* [14] */
TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8),
TNSZ("movhpd",XMMMS,8),
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16),
TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
+/* [2C] */
TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID,
INVALID,
+/* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16),
TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
+/* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16),
TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
+/* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16),
TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
+
+/* [60] */
TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
+/* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16),
TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
+/* [68] */
TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
+/* [6C] */
TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
+
+/* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID,
INVALID,
+/* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16),
TNSZ("pcmpeqd",XMM,16), INVALID,
+/* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID,
TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [8C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("cmppd",XMMP,16), INVALID,
+/* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P),
TNSZ("shufpd",XMMP,16), INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ INVALID, TNSZ("psrlw",XMM,16),
TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
+/* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16),
TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
+/* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16),
TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
+/* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16),
TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
+
+/* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16),
TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
+/* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16),
TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
+/* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16),
TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
+/* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16),
TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
+
+/* [F0] */ INVALID, TNSZ("psllw",XMM,16),
TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
+/* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16),
TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
+/* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16),
TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
+/* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16),
TNSZ("paddd",XMM,16), INVALID,
+};
+
+const instable_t dis_opAVX660F[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16),
TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
+/* [14] */
TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8),
TNSZ("vmovhpd",VEX_RM,8),
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16),
INVALID, TNSZ("vmovntpd",VEX_RM,16),
+/* [2C] */ INVALID, INVALID,
TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16),
INVALID, INVALID,
+/* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16),
TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
+/* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16),
TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
+/* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16),
TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
+
+/* [60] */
TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
+/* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16),
TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
+/* [68] */
TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
+/* [6C] */
TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
+
+/* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16),
TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
+/* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16),
TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16),
TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [8C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("vcmppd",VEX_RMRX,16), INVALID,
+/* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR),
TNSZ("vshufpd",VEX_RMRX,16), INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16),
TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
+/* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16),
TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
+/* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16),
TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
+/* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16),
TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
+
+/* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16),
TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
+/* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16),
TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
+/* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16),
TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
+/* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16),
TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
+
+/* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16),
TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
+/* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16),
TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
+/* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16),
TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
+/* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16),
TNSZ("vpaddd",VEX_RMrX,16), INVALID,
+};
+
+/*
+ * Decode table for SIMD instructions with the repnz (0xf2) prefix.
+ */
+const instable_t dis_opSIMDrepnz[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID,
INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
+/* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID,
INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8),
TNSZ("cvtsd2ss",XMM,8), INVALID,
+/* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8),
TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("cmpsd",XMMP,8), INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D4] */ INVALID, INVALID,
TNS("movdq2q",XMMXM), INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID,
TNSZ("cvtpd2dq",XMM,16),INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+const instable_t dis_opAVXF20F[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8),
TNSZ("vmovddup",VEX_MX,8), INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
+/* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8),
INVALID, INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8),
TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
+/* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8),
TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8),
INVALID, INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID,
INVALID, INVALID,
+/* [D4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID,
TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID,
INVALID, INVALID,
+/* [F4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+/*
+ * Decode table for SIMD instructions with the repz (0xf3) prefix.
+ */
+const instable_t dis_opSIMDrepz[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID,
INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
+/* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, TNSZ("sqrtss",XMM,4),
TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4),
TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
+/* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4),
TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
TNSZ("movdqu",XMM,16),
+
+/* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID,
TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
+
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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