Author: ian
Date: Wed Oct 30 14:33:15 2013
New Revision: 257383
URL: http://svnweb.freebsd.org/changeset/base/257383
Log:
Add some bare-bones support for enabling usb and usbphy clocks. This
is temporary code to keep imx development moving forward for now. In
the long run we need a SoC-independant clock management API.
Modified:
head/sys/arm/freescale/imx/imx51_ccm.c
head/sys/arm/freescale/imx/imx51_ccmreg.h
head/sys/arm/freescale/imx/imx_machdep.h
Modified: head/sys/arm/freescale/imx/imx51_ccm.c
==============================================================================
--- head/sys/arm/freescale/imx/imx51_ccm.c Wed Oct 30 14:13:15 2013
(r257382)
+++ head/sys/arm/freescale/imx/imx51_ccm.c Wed Oct 30 14:33:15 2013
(r257383)
@@ -83,6 +83,7 @@ __FBSDID("$FreeBSD$");
#include <arm/freescale/imx/imx51_ccmvar.h>
#include <arm/freescale/imx/imx51_ccmreg.h>
#include <arm/freescale/imx/imx51_dpllreg.h>
+#include <arm/freescale/imx/imx_machdep.h>
#define IMXCCMDEBUG
#undef IMXCCMDEBUG
@@ -473,3 +474,78 @@ imx51_get_clk_gating(int clk_src)
return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03);
}
+/*
+ * Code from here down is temporary, in lieu of a SoC-independent clock API.
+ */
+
+void
+imx_ccm_usb_enable(device_t dev)
+{
+ uint32_t regval;
+
+ /*
+ * Select PLL2 as the source for the USB clock.
+ * The default is PLL3, but U-boot changes it to PLL2.
+ */
+ regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1);
+ regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK;
+ regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT;
+ bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval);
+
+ /*
+ * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2.
+ */
+ regval = bus_read_4(ccm_softc->res[0], CCMC_CSCDR1);
+ regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK;
+ regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK;
+ regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT;
+ regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT;
+ bus_write_4(ccm_softc->res[0], CCMC_CSCDR1, regval);
+
+ /*
+ * The same two clocks gates are used on imx51 and imx53.
+ */
+ imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS);
+ imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS);
+}
+
+void
+imx_ccm_usbphy_enable(device_t dev)
+{
+ uint32_t regval;
+
+ /*
+ * Select PLL3 as the source for the USBPHY clock. U-boot does this
+ * only for imx53, but the bit exists on imx51. That seems a bit
+ * strange, but we'll go with it until more is known.
+ */
+ if (imx_soc_type() == IMXSOC_53) {
+ regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1);
+ regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT;
+ bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval);
+ }
+
+ /*
+ * For the imx51 there's just one phy gate control, enable it.
+ */
+ if (imx_soc_type() == IMXSOC_51) {
+ imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS);
+ return;
+ }
+
+ /*
+ * For imx53 we don't have a full set of clock defines yet, but the
+ * datasheet says:
+ * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable)
+ * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable)
+ *
+ * We should use the fdt data for the device to figure out which of
+ * the two we're working on, but for now just turn them both on.
+ */
+ if (imx_soc_type() == IMXSOC_53) {
+ imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS);
+ imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS);
+ return;
+ }
+}
+
Modified: head/sys/arm/freescale/imx/imx51_ccmreg.h
==============================================================================
--- head/sys/arm/freescale/imx/imx51_ccmreg.h Wed Oct 30 14:13:15 2013
(r257382)
+++ head/sys/arm/freescale/imx/imx51_ccmreg.h Wed Oct 30 14:33:15 2013
(r257383)
@@ -114,12 +114,20 @@
#define CCMC_CSCMR1 0x001c
#define CSCMR1_UART_CLK_SEL_SHIFT 24
#define CSCMR1_UART_CLK_SEL_MASK 0x03000000
+#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26
+#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000
+#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22
+#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000
#define CCMC_CSCMR2 0x0020
#define CCMC_CSCDR1 0x0024
#define CSCDR1_UART_CLK_PRED_SHIFT 3
#define CSCDR1_UART_CLK_PRED_MASK 0x00000038
#define CSCDR1_UART_CLK_PODF_SHIFT 0
#define CSCDR1_UART_CLK_PODF_MASK 0x00000007
+#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8
+#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700
+#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6
+#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0
#define CCMC_CS1CDR 0x0028
#define CCMC_CS2CDR 0x002c
#define CCMC_CDCDR 0x0030
Modified: head/sys/arm/freescale/imx/imx_machdep.h
==============================================================================
--- head/sys/arm/freescale/imx/imx_machdep.h Wed Oct 30 14:13:15 2013
(r257382)
+++ head/sys/arm/freescale/imx/imx_machdep.h Wed Oct 30 14:33:15 2013
(r257383)
@@ -56,5 +56,21 @@ u_int imx_soc_family(void);
void imx_devmap_init(void);
+/*
+ * We need a clock management system that works across unrelated SoCs and
+ * devices. For now, to keep imx development moving, define some barebones
+ * functionality that can be shared within the imx family by having each SoC
+ * implement functions with a common name.
+ *
+ * The usb enable functions are best-effort. They turn on the usb otg, host,
+ * and phy clocks in a SoC-specific manner, but it may take a lot more than
that
+ * to make usb work on a given board. In particular, it can require specific
+ * pinmux setup of gpio pins connected to external phy parts, voltage
regulators
+ * and overcurrent detectors, and so on. On such boards, u-boot or other early
+ * board setup code has to handle those things.
+ */
+void imx_ccm_usb_enable(device_t _usbdev);
+void imx_ccm_usbphy_enable(device_t _phydev);
+
#endif
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