Author: dim
Date: Mon Oct 7 16:33:16 2013
New Revision: 256112
URL: http://svnweb.freebsd.org/changeset/base/256112
Log:
Add support for assembling and disassembling Intel Random Number
Generator extensions (e.g. the 'rdrand' mnemonic) to our copy of
binutils.
Approved by: re (kib)
Obtained from: OpenBSD, via pfg
MFC after: 1 week
Modified:
head/contrib/binutils/opcodes/i386-dis.c
head/contrib/binutils/opcodes/i386-opc.h
head/contrib/binutils/opcodes/i386-opc.tbl
head/contrib/binutils/opcodes/i386-tbl.h
Modified: head/contrib/binutils/opcodes/i386-dis.c
==============================================================================
--- head/contrib/binutils/opcodes/i386-dis.c Mon Oct 7 15:28:08 2013
(r256111)
+++ head/contrib/binutils/opcodes/i386-dis.c Mon Oct 7 16:33:16 2013
(r256112)
@@ -6438,14 +6438,22 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSE
static void
OP_VMX (int bytemode, int sizeflag)
{
- used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
- if (prefixes & PREFIX_DATA)
- strcpy (obuf, "vmclear");
- else if (prefixes & PREFIX_REPZ)
- strcpy (obuf, "vmxon");
+ if (modrm.mod == 3)
+ {
+ strcpy (obuf, "rdrand");
+ OP_E (v_mode, sizeflag);
+ }
else
- strcpy (obuf, "vmptrld");
- OP_E (bytemode, sizeflag);
+ {
+ used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
+ if (prefixes & PREFIX_DATA)
+ strcpy (obuf, "vmclear");
+ else if (prefixes & PREFIX_REPZ)
+ strcpy (obuf, "vmxon");
+ else
+ strcpy (obuf, "vmptrld");
+ OP_E (bytemode, sizeflag);
+ }
}
static void
Modified: head/contrib/binutils/opcodes/i386-opc.h
==============================================================================
--- head/contrib/binutils/opcodes/i386-opc.h Mon Oct 7 15:28:08 2013
(r256111)
+++ head/contrib/binutils/opcodes/i386-opc.h Mon Oct 7 16:33:16 2013
(r256112)
@@ -79,6 +79,7 @@ typedef struct template
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
+#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */
/* SSE4.1/4.2 Instructions required */
#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
@@ -87,7 +88,7 @@ typedef struct template
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
- |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL)
+ |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
Modified: head/contrib/binutils/opcodes/i386-opc.tbl
==============================================================================
--- head/contrib/binutils/opcodes/i386-opc.tbl Mon Oct 7 15:28:08 2013
(r256111)
+++ head/contrib/binutils/opcodes/i386-opc.tbl Mon Oct 7 16:33:16 2013
(r256112)
@@ -1502,3 +1502,21 @@ xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|N
// INVPCID
invpcid, 2, 0x660f3882, None, CpuNo64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
invpcid, 2, 0x660f3882, None, Cpu64,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, {
BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
+
+// Intel AES extensions
+aesdec, 2, 0x660f38de, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, {
RegXMM|LLongMem, RegXMM }
+aesdeclast, 2, 0x660f38df, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, {
RegXMM|LLongMem, RegXMM }
+aesenc, 2, 0x660f38dc, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, {
RegXMM|LLongMem, RegXMM }
+aesenclast, 2, 0x660f38dd, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, {
RegXMM|LLongMem, RegXMM }
+aesimc, 2, 0x660f38db, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, {
RegXMM|LLongMem, RegXMM }
+aeskeygenassist, 3, 0x660f3adf, None, CpuAES,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8,
RegXMM|LLongMem, RegXMM }
+
+// Intel Carry-less Multiplication extensions
+pclmulqdq, 3, 0x660f3a44, None, CpuPCLMUL,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8,
RegXMM|LLongMem, RegXMM }
+pclmullqlqdq, 2, 0x660f3a44, 0x0, CpuPCLMUL,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, {
RegXMM|LLongMem, RegXMM }
+pclmulhqlqdq, 2, 0x660f3a44, 0x1, CpuPCLMUL,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, {
RegXMM|LLongMem, RegXMM }
+pclmullqhqdq, 2, 0x660f3a44, 0x10, CpuPCLMUL,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, {
RegXMM|LLongMem, RegXMM }
+pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL,
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, {
RegXMM|LLongMem, RegXMM }
+
+// Intel Random Number Generator extensions
+rdrand, 1, 0x0fc7, 0x6, CpuRdRnd,
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
Modified: head/contrib/binutils/opcodes/i386-tbl.h
==============================================================================
--- head/contrib/binutils/opcodes/i386-tbl.h Mon Oct 7 15:28:08 2013
(r256111)
+++ head/contrib/binutils/opcodes/i386-tbl.h Mon Oct 7 16:33:16 2013
(r256112)
@@ -4374,6 +4374,11 @@ const template i386_optab[] =
Modrm|IgnoreSize|NoSuf|ImmExt,
{ RegXMM|LLongMem,
RegXMM } },
+
+ /* Intel Random Number Generator extensions */
+ {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
+ Modrm|NoSuf,
+ { Reg16|Reg32|Reg64 } },
{ NULL, 0, 0, 0, 0, 0, { 0 } }
};
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