Author: imp
Date: Fri Jun 29 04:18:52 2012
New Revision: 237742
URL: http://svn.freebsd.org/changeset/base/237742
Log:
Initital support for AT91SAM9X25 SoC and the SAM9X25-EK evaluation
board. Much work remains.
Added:
head/sys/arm/at91/at91sam9x25.c (contents, props changed)
head/sys/arm/at91/at91sam9x25reg.h (contents, props changed)
head/sys/arm/at91/board_sam9x25ek.c (contents, props changed)
head/sys/arm/at91/std.sam9x25ek (contents, props changed)
head/sys/arm/conf/SAM9X25EK (contents, props changed)
head/sys/arm/conf/SAM9X25EK.hints (contents, props changed)
Added: head/sys/arm/at91/at91sam9x25.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/at91sam9x25.c Fri Jun 29 04:18:52 2012
(r237742)
@@ -0,0 +1,343 @@
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ * Copyright (c) 2010 Greg Ansley. All rights reserved.
+ * Copyright (c) 2012 M. Warner Losh.. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+
+#include <arm/at91/at91var.h>
+#include <arm/at91/at91_aicreg.h>
+#include <arm/at91/at91sam9x25reg.h>
+#include <arm/at91/at91_pmcreg.h>
+#include <arm/at91/at91_pmcvar.h>
+
+struct at91sam9x25_softc {
+ device_t dev;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_sh;
+ bus_space_handle_t sc_sys_sh;
+ bus_space_handle_t sc_aic_sh;
+ bus_space_handle_t sc_dbg_sh;
+ bus_space_handle_t sc_matrix_sh;
+};
+
+/*
+ * Standard priority levels for the system. 0 is lowest and 7 is highest.
+ * These values are the ones Atmel uses for its Linux port
+ */
+static const int at91_irq_prio[32] =
+{
+ 7, /* Advanced Interrupt Controller */
+ 7, /* System Peripherals */
+ 1, /* Parallel IO Controller A */
+ 1, /* Parallel IO Controller B */
+ 1, /* Parallel IO Controller C */
+ 0, /* Analog-to-Digital Converter */
+ 5, /* USART 0 */
+ 5, /* USART 1 */
+ 5, /* USART 2 */
+ 0, /* Multimedia Card Interface */
+ 2, /* USB Device Port */
+ 6, /* Two-Wire Interface */
+ 5, /* Serial Peripheral Interface 0 */
+ 5, /* Serial Peripheral Interface 1 */
+ 5, /* Serial Synchronous Controller */
+ 0, /* (reserved) */
+ 0, /* (reserved) */
+ 0, /* Timer Counter 0 */
+ 0, /* Timer Counter 1 */
+ 0, /* Timer Counter 2 */
+ 2, /* USB Host port */
+ 3, /* Ethernet */
+ 0, /* Image Sensor Interface */
+ 5, /* USART 3 */
+ 5, /* USART 4 */
+ 5, /* USART 5 */
+ 0, /* Timer Counter 3 */
+ 0, /* Timer Counter 4 */
+ 0, /* Timer Counter 5 */
+ 0, /* Advanced Interrupt Controller IRQ0 */
+ 0, /* Advanced Interrupt Controller IRQ1 */
+ 0, /* Advanced Interrupt Controller IRQ2 */
+};
+
+#define DEVICE(_name, _id, _unit) \
+ { \
+ _name, _unit, \
+ AT91SAM9X25_ ## _id ##_BASE, \
+ AT91SAM9X25_ ## _id ## _SIZE, \
+ AT91SAM9X25_IRQ_ ## _id \
+ }
+
+static const struct cpu_devs at91_devs[] =
+{
+ DEVICE("at91_pmc", PMC, 0),
+ DEVICE("at91_wdt", WDT, 0),
+ DEVICE("at91_rst", RSTC, 0),
+ DEVICE("at91_pit", PIT, 0),
+ DEVICE("at91_pio", PIOA, 0),
+ DEVICE("at91_pio", PIOB, 1),
+ DEVICE("at91_pio", PIOC, 2),
+ DEVICE("at91_twi", TWI0, 0),
+ DEVICE("at91_twi", TWI1, 1),
+ DEVICE("at91_twi", TWI2, 2),
+ DEVICE("at91_mci", HSMCI0, 0),
+ DEVICE("at91_mci", HSMCI1, 1),
+ DEVICE("uart", DBGU, 0),
+ DEVICE("uart", USART0, 1),
+ DEVICE("uart", USART1, 2),
+ DEVICE("uart", USART2, 3),
+ DEVICE("uart", USART3, 4),
+ DEVICE("spi", SPI0, 0),
+ DEVICE("spi", SPI1, 1),
+ DEVICE("macb", EMAC0, 0),
+ DEVICE("macb", EMAC1, 0),
+ DEVICE("nand", NAND, 0),
+ DEVICE("ohci", OHCI, 0),
+ DEVICE("ehci", EHCI, 0),
+ { 0, 0, 0, 0, 0 }
+};
+
+static void
+at91_add_child(device_t dev, int prio, const char *name, int unit,
+ bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2)
+{
+ device_t kid;
+ struct at91_ivar *ivar;
+
+ kid = device_add_child_ordered(dev, prio, name, unit);
+ if (kid == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return;
+ }
+ ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (ivar == NULL) {
+ device_delete_child(dev, kid);
+ printf("Can't add alloc ivar\n");
+ return;
+ }
+ device_set_ivars(kid, ivar);
+ resource_list_init(&ivar->resources);
+ if (irq0 != -1) {
+ bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
+ if (irq0 != AT91SAM9X25_IRQ_SYSTEM)
+ at91_pmc_clock_add(device_get_nameunit(kid), irq0, 0);
+ }
+ if (irq1 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
+ if (irq2 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
+ if (addr != 0 && addr < AT91SAM9X25_BASE)
+ addr += AT91SAM9X25_BASE;
+ if (addr != 0)
+ bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
+}
+
+static void
+at91_cpu_add_builtin_children(device_t dev)
+{
+ int i;
+ const struct cpu_devs *walker;
+
+ for (i = 1, walker = at91_devs; walker->name; i++, walker++) {
+ at91_add_child(dev, i, walker->name, walker->unit,
+ walker->mem_base, walker->mem_len, walker->irq0,
+ walker->irq1, walker->irq2);
+ }
+}
+
+static uint32_t
+at91_pll_outa(int freq)
+{
+
+ switch (freq / 10000000) {
+ case 747 ... 801: return ((1 << 29) | (0 << 14));
+ case 697 ... 746: return ((1 << 29) | (1 << 14));
+ case 647 ... 696: return ((1 << 29) | (2 << 14));
+ case 597 ... 646: return ((1 << 29) | (3 << 14));
+ case 547 ... 596: return ((1 << 29) | (1 << 14));
+ case 497 ... 546: return ((1 << 29) | (2 << 14));
+ case 447 ... 496: return ((1 << 29) | (3 << 14));
+ case 397 ... 446: return ((1 << 29) | (4 << 14));
+ default: return (1 << 29);
+ }
+}
+
+static uint32_t
+at91_pll_outb(int freq)
+{
+
+ return (0);
+}
+
+static void
+at91_identify(driver_t *drv, device_t parent)
+{
+
+ if (soc_data.type == AT91_T_SAM9X5 && soc_data.subtype ==
AT91_ST_SAM9X25) {
+ at91_add_child(parent, 0, "at91sam9x25", 0, 0, 0, -1, 0, 0);
+ at91_cpu_add_builtin_children(parent);
+ }
+}
+
+static int
+at91_probe(device_t dev)
+{
+
+ device_set_desc(dev, "AT91SAM9X25");
+ return (0);
+}
+
+static int
+at91_attach(device_t dev)
+{
+ struct at91_pmc_clock *clk;
+ struct at91sam9x25_softc *sc = device_get_softc(dev);
+ int i;
+
+ struct at91_softc *at91sc = device_get_softc(device_get_parent(dev));
+
+ sc->sc_st = at91sc->sc_st;
+ sc->sc_sh = at91sc->sc_sh;
+ sc->dev = dev;
+
+ /*
+ * XXX These values work for the RM9200, SAM926[01], and SAM9X25
+ * will have to fix this when we want to support anything else. XXX
+ */
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_SYS_BASE,
+ AT91SAM9X25_SYS_SIZE, &sc->sc_sys_sh) != 0)
+ panic("Enable to map system registers");
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_DBGU_BASE,
+ AT91SAM9X25_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
+ panic("Enable to map DBGU registers");
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_AIC_BASE,
+ AT91SAM9X25_AIC_SIZE, &sc->sc_aic_sh) != 0)
+ panic("Enable to map system registers");
+
+ /* XXX Hack to tell atmelarm about the AIC */
+ at91sc->sc_aic_sh = sc->sc_aic_sh;
+ at91sc->sc_irq_system = AT91SAM9X25_IRQ_SYSTEM;
+
+ for (i = 0; i < 32; i++) {
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
+ i * 4, i);
+ /* Priority. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,
+ at91_irq_prio[i]);
+ if (i < 8)
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR,
+ 1);
+ }
+
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32);
+ /* No debug. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0);
+ /* Disable and clear all interrupts. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
+
+ /* Disable all interrupts for DBGU */
+ bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh,
+ AT91SAM9X25_MATRIX_BASE, AT91SAM9X25_MATRIX_SIZE,
+ &sc->sc_matrix_sh) != 0)
+ panic("Enable to map matrix registers");
+
+#if 0 /* wrong, placeholder */
+ /* activate NAND*/
+ i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh,
+ AT91SAM9X25_EBICSA);
+ bus_space_write_4(sc->sc_st, sc->sc_matrix_sh,
+ AT91SAM9X25_EBICSA,
+ i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+#endif
+
+ /* Update USB device port clock info */
+ clk = at91_pmc_clock_ref("udpck");
+ clk->pmc_mask = PMC_SCER_UDP_SAM9;
+ at91_pmc_clock_deref(clk);
+
+ /* Update USB host port clock info */
+ clk = at91_pmc_clock_ref("uhpck");
+ clk->pmc_mask = PMC_SCER_UHP_SAM9;
+ at91_pmc_clock_deref(clk);
+
+ /* Each SOC has different PLL contraints */
+ clk = at91_pmc_clock_ref("plla");
+ clk->pll_min_in = SAM9X25_PLL_A_MIN_IN_FREQ; /* 2 MHz */
+ clk->pll_max_in = SAM9X25_PLL_A_MAX_IN_FREQ; /* 32 MHz */
+ clk->pll_min_out = SAM9X25_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
+ clk->pll_max_out = SAM9X25_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
+ clk->pll_mul_shift = SAM9X25_PLL_A_MUL_SHIFT;
+ clk->pll_mul_mask = SAM9X25_PLL_A_MUL_MASK;
+ clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT;
+ clk->pll_div_mask = SAM9X25_PLL_A_DIV_MASK;
+ clk->set_outb = at91_pll_outa;
+ at91_pmc_clock_deref(clk);
+
+ clk = at91_pmc_clock_ref("pllb");
+ clk->pll_min_in = SAM9X25_PLL_B_MIN_IN_FREQ; /* 2 MHz */
+ clk->pll_max_in = SAM9X25_PLL_B_MAX_IN_FREQ; /* 32 MHz */
+ clk->pll_min_out = SAM9X25_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
+ clk->pll_max_out = SAM9X25_PLL_B_MAX_OUT_FREQ; /* 100 MHz */
+ clk->pll_mul_shift = SAM9X25_PLL_B_MUL_SHIFT;
+ clk->pll_mul_mask = SAM9X25_PLL_B_MUL_MASK;
+ clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT;
+ clk->pll_div_mask = SAM9X25_PLL_B_DIV_MASK;
+ clk->set_outb = at91_pll_outb;
+ at91_pmc_clock_deref(clk);
+ return (0);
+}
+
+static device_method_t at91sam9x25_methods[] = {
+ DEVMETHOD(device_probe, at91_probe),
+ DEVMETHOD(device_attach, at91_attach),
+ DEVMETHOD(device_identify, at91_identify),
+ {0, 0},
+};
+
+static driver_t at91sam9x25_driver = {
+ "at91sam9x25",
+ at91sam9x25_methods,
+ sizeof(struct at91sam9x25_softc),
+};
+
+static devclass_t at91sam9x25_devclass;
+
+DRIVER_MODULE(at91sam9x25, atmelarm, at91sam9x25_driver, at91sam9x25_devclass,
0, 0);
Added: head/sys/arm/at91/at91sam9x25reg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/at91sam9x25reg.h Fri Jun 29 04:18:52 2012
(r237742)
@@ -0,0 +1,316 @@
+/*-
+ * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
+ * Copyright (c) 2010 Greg Ansley. All rights reserved.
+ * Copyright (c) 2012 M. Warener Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef AT91SAM9X25REG_H_
+#define AT91SAM9X25REG_H_
+
+#ifndef AT91SAM9X25_MASTER_CLOCK
+#define AT91SAM9X25_MASTER_CLOCK ((18432000 * 43)/6)
+#endif
+
+/* Chip Specific limits */
+#define SAM9X25_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
+#define SAM9X25_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
+#define SAM9X25_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
+#define SAM9X25_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
+#define SAM9X25_PLL_A_MUL_SHIFT 16
+#define SAM9X25_PLL_A_MUL_MASK 0xFF
+#define SAM9X25_PLL_A_DIV_SHIFT 0
+#define SAM9X25_PLL_A_DIV_MASK 0xFF
+
+#define SAM9X25_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */
+#define SAM9X25_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */
+#define SAM9X25_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */
+#define SAM9X25_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */
+#define SAM9X25_PLL_B_MUL_SHIFT 16
+#define SAM9X25_PLL_B_MUL_MASK 0x3F
+#define SAM9X25_PLL_B_DIV_SHIFT 0
+#define SAM9X25_PLL_B_DIV_MASK 0xFF
+
+/*
+ * Memory map, from datasheet :
+ * 0x00000000 - 0x0ffffffff : Internal Memories
+ * 0x10000000 - 0x1ffffffff : Chip Select 0
+ * 0x20000000 - 0x2ffffffff : Chip Select 1 DDR2/LPDDR/SDR/LPSDR
+ * 0x30000000 - 0x3ffffffff : Chip Select 2
+ * 0x40000000 - 0x4ffffffff : Chip Select 3 NAND Flash
+ * 0x50000000 - 0x5ffffffff : Chip Select 4
+ * 0x60000000 - 0x6ffffffff : Chip Select 5
+ * 0x70000000 - 0xeffffffff : Undefined (Abort)
+ * 0xf0000000 - 0xfffffffff : Peripherals
+ */
+
+#define AT91_CHIPSELECT_0 0x10000000
+#define AT91_CHIPSELECT_1 0x20000000
+#define AT91_CHIPSELECT_2 0x30000000
+#define AT91_CHIPSELECT_3 0x40000000
+#define AT91_CHIPSELECT_4 0x50000000
+#define AT91_CHIPSELECT_5 0x60000000
+
+#define AT91SAM9X25_BASE 0xd0000000
+
+#define AT91SAM9X25_EMAC_SIZE 0x4000
+#define AT91SAM9X25_EMAC0_BASE 0x802c000
+#define AT91SAM9X25_EMAC0_SIZE AT91SAM9X25_EMAC_SIZE
+#define AT91SAM9X25_EMAC1_BASE 0x8030000
+#define AT91SAM9X25_EMAC1_SIZE AT91SAM9X25_EMAC_SIZE
+
+#define AT91SAM9X25_RSTC_BASE 0xffffe00
+#define AT91SAM9X25_RSTC_SIZE 0x10
+
+/* USART*/
+
+#define AT91SAM9X25_USART_SIZE 0x4000
+#define AT91SAM9X25_USART0_BASE 0x801c000
+#define AT91SAM9X25_USART0_PDC 0x801c100
+#define AT91SAM9X25_USART0_SIZE AT91SAM9X25_USART_SIZE
+#define AT91SAM9X25_USART1_BASE 0x8020000
+#define AT91SAM9X25_USART1_PDC 0x8020100
+#define AT91SAM9X25_USART1_SIZE AT91SAM9X25_USART_SIZE
+#define AT91SAM9X25_USART2_BASE 0x8024000
+#define AT91SAM9X25_USART2_PDC 0x8024100
+#define AT91SAM9X25_USART2_SIZE AT91SAM9X25_USART_SIZE
+#define AT91SAM9X25_USART3_BASE 0x8028000
+#define AT91SAM9X25_USART3_PDC 0x8028100
+#define AT91SAM9X25_USART3_SIZE AT91SAM9X25_USART_SIZE
+
+/*TC*/
+#define AT91SAM9X25_TC0_BASE 0x8008000
+#define AT91SAM9X25_TC0_SIZE 0x4000
+#define AT91SAM9X25_TC0C0_BASE 0x8008000
+#define AT91SAM9X25_TC0C1_BASE 0x8008040
+#define AT91SAM9X25_TC0C2_BASE 0x8008080
+
+#define AT91SAM9X25_TC1_BASE 0x800c000
+#define AT91SAM9X25_TC1_SIZE 0x4000
+
+/*SPI*/
+
+#define AT91SAM9X25_SPI0_BASE 0x0000000
+
+#define AT91SAM9X25_SPI0_SIZE 0x4000
+
+#define AT91SAM9X25_SPI1_BASE 0x0004000
+#define AT91SAM9X25_SPI1_SIZE 0x4000
+
+/* System Registers */
+#define AT91SAM9X25_SYS_BASE 0xffff000
+#define AT91SAM9X25_SYS_SIZE 0x1000
+
+#define AT91SAM9X25_MATRIX_BASE 0xfffde00
+#define AT91SAM9X25_MATRIX_SIZE 0x200
+
+#define AT91SAM9X25_DBGU_BASE 0xffff200
+#define AT91SAM9X25_DBGU_SIZE 0x200
+
+/*
+ * PIO
+ */
+#define AT91SAM9X25_PIOA_BASE 0xffff400
+#define AT91SAM9X25_PIOA_SIZE 0x200
+#define AT91SAM9X25_PIOB_BASE 0xffff600
+#define AT91SAM9X25_PIOB_SIZE 0x200
+#define AT91SAM9X25_PIOC_BASE 0xffff800
+#define AT91SAM9X25_PIOC_SIZE 0x200
+
+#define AT91RM92_PMC_BASE 0xffffc00
+#define AT91RM92_PMC_SIZE 0x100
+/* IRQs : */
+/*XXX FIXME XXX
+ * 0: AIC
+ * 1: System peripheral (System timer, RTC, DBGU)
+ * 2: PIO Controller A,B
+ * 3: PIO Controller C,D
+ * 4: SMD Soft Modem
+ * 5: USART 0
+ * 6: USART 1
+ * 7: USART 2
+ * 8: USART 3
+ * 9: Two-wirte interface
+ * 10: Two-wirte interface
+ * 11: Two-wirte interface
+ * 12: HSMCI Interface
+ * 13: SPI 0
+ * 14: SPI 1
+ * 15: UART0
+ * 16: UART1
+ * 17: Timer Counter 0,1
+ * 18: PWM
+ * 19: ADC
+ * 20: DMAC 0
+ * 21: DMAC 1
+ * 22: UHPHS - USB Host controller
+ * 23: UDPHS - USB Device Controller
+ * 24: EMAC0
+ * 25: Reserved
+ * 26: HSMCI1
+ * 27: EMAC1
+ * 28: SSC
+ * 29: CAN0
+ * 30: CAN1
+ * 31: AIC IRQ
+ */
+
+#define AT91SAM9X25_IRQ_AIC 0
+#define AT91SAM9X25_IRQ_SYSTEM 1
+#define AT91SAM9X25_IRQ_PIOAB 2
+#define AT91SAM9X25_IRQ_PIOCD 3
+#define AT91SAM9X25_IRQ_SMD 4
+#define AT91SAM9X25_IRQ_USART0 5
+#define AT91SAM9X25_IRQ_USART1 6
+#define AT91SAM9X25_IRQ_USART2 7
+#define AT91SAM9X25_IRQ_USART3 8
+#define AT91SAM9X25_IRQ_TWI0 9
+#define AT91SAM9X25_IRQ_TWI1 10
+#define AT91SAM9X25_IRQ_TWI2 11
+#define AT91SAM9X25_IRQ_HSMCI0 12
+#define AT91SAM9X25_IRQ_SPI0 13
+#define AT91SAM9X25_IRQ_SPI1 14
+#define AT91SAM9X25_IRQ_UART0 15
+#define AT91SAM9X25_IRQ_UART1 16
+#define AT91SAM9X25_IRQ_TC01 17
+#define AT91SAM9X25_IRQ_PWM 18
+#define AT91SAM9X25_IRQ_ADC 19
+#define AT91SAM9X25_IRQ_DMAC0 20
+#define AT91SAM9X25_IRQ_DMAC1 21
+#define AT91SAM9X25_IRQ_UHPHS 22
+#define AT91SAM9X25_IRQ_UDPHS 23
+#define AT91SAM9X25_IRQ_EMAC0 24
+#define AT91SAM9X25_IRQ_HSMCI1 26
+#define AT91SAM9X25_IRQ_EMAC1 27
+#define AT91SAM9X25_IRQ_SSC 28
+#define AT91SAM9X25_IRQ_CAN0 29
+#define AT91SAM9X25_IRQ_CAN1 30
+#define AT91SAM9X25_IRQ_AICBASE 31
+
+/* Alias */
+#define AT91SAM9X25_IRQ_DBGU AT91SAM9X25_IRQ_SYSTEM
+#define AT91SAM9X25_IRQ_PMC AT91SAM9X25_IRQ_SYSTEM
+#define AT91SAM9X25_IRQ_WDT AT91SAM9X25_IRQ_SYSTEM
+#define AT91SAM9X25_IRQ_PIT AT91SAM9X25_IRQ_SYSTEM
+#define AT91SAM9X25_IRQ_RSTC AT91SAM9X25_IRQ_SYSTEM
+#define AT91SAM9X25_IRQ_OHCI AT91SAM9X25_IRQ_UHPHS
+#define AT91SAM9X25_IRQ_EHCI AT91SAM9X25_IRQ_UHPHS
+#define AT91SAM9X25_IRQ_PIOA AT91SAM9X25_IRQ_PIOAB
+#define AT91SAM9X25_IRQ_PIOB AT91SAM9X25_IRQ_PIOAB
+#define AT91SAM9X25_IRQ_PIOC AT91SAM9X25_IRQ_PIOCD
+#define AT91SAM9X25_IRQ_NAND (-1)
+
+#define AT91SAM9X25_AIC_BASE 0xffff000
+#define AT91SAM9X25_AIC_SIZE 0x200
+
+/* Timer */
+
+#define AT91SAM9X25_WDT_BASE 0xffffd40
+#define AT91SAM9X25_WDT_SIZE 0x10
+
+#define AT91SAM9X25_PIT_BASE 0xffffd30
+#define AT91SAM9X25_PIT_SIZE 0x10
+
+#define AT91SAM9X25_SMC_BASE 0xfffea00
+#define AT91SAM9X25_SMC_SIZE 0x200
+
+#define AT91SAM9X25_PMC_BASE 0xffffc00
+#define AT91SAM9X25_PMC_SIZE 0x100
+
+#define AT91SAM9X25_UDPHS_BASE 0x803c000
+#define AT91SAM9X25_UDPHS_SIZE 0x4000
+
+#define AT91SAM9X25_HSMCI_SIZE 0x4000
+#define AT91SAM9X25_HSMCI0_BASE 0x0008000
+#define AT91SAM9X25_HSMCI0_SIZE AT91SAM9X25_HSMCI_SIZE
+#define AT91SAM9X25_HSMCI1_BASE 0x000c000
+#define AT91SAM9X25_HSMCI1_SIZE AT91SAM9X25_HSMCI_SIZE
+
+#define AT91SAM9X25_TWI_SIZE 0x4000
+#define AT91SAM9X25_TWI0_BASE 0xffaC000
+#define AT91SAM9X25_TWI0_SIZE AT91SAM9X25_TWI_SIZE
+#define AT91SAM9X25_TWI1_BASE 0xffaC000
+#define AT91SAM9X25_TWI1_SIZE AT91SAM9X25_TWI_SIZE
+#define AT91SAM9X25_TWI2_BASE 0xffaC000
+#define AT91SAM9X25_TWI2_SIZE AT91SAM9X25_TWI_SIZE
+
+/* XXX Needs to be carfully coordinated with
+ * other * soc's so phyical and vm address
+ * mapping are unique. XXX
+ */
+#define AT91SAM9X25_OHCI_BASE 0xdfc00000 /* SAME as 9c40 */
+#define AT91SAM9X25_OHCI_PA_BASE 0x00600000
+#define AT91SAM9X25_OHCI_SIZE 0x00100000
+
+#define AT91SAM9X25_EHCI_BASE 0xdfd00000
+#define AT91SAM9X25_EHCI_PA_BASE 0x00700000
+#define AT91SAM9X25_EHCI_SIZE 0x00100000
+
+#define AT91SAM9X25_NAND_BASE 0xe0000000
+#define AT91SAM9X25_NAND_PA_BASE 0x40000000
+#define AT91SAM9X25_NAND_SIZE 0x10000000
+
+
+/* SDRAMC */
+#define AT91SAM9X25_SDRAMC_BASE 0xfffea00 /* SAME as SMC?
*/
+#define AT91SAM9X25_SDRAMC_MR 0x00
+#define AT91SAM9X25_SDRAMC_MR_MODE_NORMAL 0
+#define AT91SAM9X25_SDRAMC_MR_MODE_NOP 1
+#define AT91SAM9X25_SDRAMC_MR_MODE_PRECHARGE 2
+#define AT91SAM9X25_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
+#define AT91SAM9X25_SDRAMC_MR_MODE_REFRESH 4
+#define AT91SAM9X25_SDRAMC_TR 0x04
+#define AT91SAM9X25_SDRAMC_CR 0x08
+#define AT91SAM9X25_SDRAMC_CR_NC_8 0x0
+#define AT91SAM9X25_SDRAMC_CR_NC_9 0x1
+#define AT91SAM9X25_SDRAMC_CR_NC_10 0x2
+#define AT91SAM9X25_SDRAMC_CR_NC_11 0x3
+#define AT91SAM9X25_SDRAMC_CR_NC_MASK 0x00000003
+#define AT91SAM9X25_SDRAMC_CR_NR_11 0x0
+#define AT91SAM9X25_SDRAMC_CR_NR_12 0x4
+#define AT91SAM9X25_SDRAMC_CR_NR_13 0x8
+#define AT91SAM9X25_SDRAMC_CR_NR_RES 0xc
+#define AT91SAM9X25_SDRAMC_CR_NR_MASK 0x0000000c
+#define AT91SAM9X25_SDRAMC_CR_NB_2 0x00
+#define AT91SAM9X25_SDRAMC_CR_NB_4 0x10
+#define AT91SAM9X25_SDRAMC_CR_DBW_16 0x80
+#define AT91SAM9X25_SDRAMC_CR_NB_MASK 0x00000010
+#define AT91SAM9X25_SDRAMC_CR_NCAS_MASK 0x00000060
+#define AT91SAM9X25_SDRAMC_CR_TWR_MASK 0x00000780
+#define AT91SAM9X25_SDRAMC_CR_TRC_MASK 0x00007800
+#define AT91SAM9X25_SDRAMC_CR_TRP_MASK 0x00078000
+#define AT91SAM9X25_SDRAMC_CR_TRCD_MASK 0x00780000
+#define AT91SAM9X25_SDRAMC_CR_TRAS_MASK 0x07800000
+#define AT91SAM9X25_SDRAMC_CR_TXSR_MASK 0x78000000
+#define AT91SAM9X25_SDRAMC_HSR 0x0c
+#define AT91SAM9X25_SDRAMC_LPR 0x10
+#define AT91SAM9X25_SDRAMC_IER 0x14
+#define AT91SAM9X25_SDRAMC_IDR 0x18
+#define AT91SAM9X25_SDRAMC_IMR 0x1c
+#define AT91SAM9X25_SDRAMC_ISR 0x20
+#define AT91SAM9X25_SDRAMC_MDR 0x24
+
+#endif /* AT91SAM9X25REG_H_*/
+
Added: head/sys/arm/at91/board_sam9x25ek.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/board_sam9x25ek.c Fri Jun 29 04:18:52 2012
(r237742)
@@ -0,0 +1,125 @@
+/*-
+ * Copyright (c) 2009 Greg Ansley. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * This board file can be used for both:
+ * SAM9X26EK board
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <arm/at91/at91board.h>
+#include <arm/at91/at91reg.h>
+#include <arm/at91/at91var.h>
+#include <arm/at91/at91sam9g20reg.h>
+#include <arm/at91/at91_piovar.h>
+#include <arm/at91/at91_pio_sam9g20.h>
+//#include <arm/at91/at91_led.h>
+
+long
+board_init(void)
+{
+#if 0
+ /* PIOB's A periph: Turn USART 0's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1);
+
+ /* PIOB's A periph: Turn USART 0's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB4_TXD0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB5_RXD0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB22_DSR0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB23_DCD0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB24_DTR0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB25_RI0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB26_RTS0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB27_CTS0, 0);
+
+ /* PIOB's A periph: Turn USART 1's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB6_TXD1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB7_RXD1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0);
+
+ /* TWI Two-wire Serial Data */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1);
+
+#if 1
+ /*
+ * Turn off Clock to DataFlash, conflicts with MCI clock.
+ */
+ at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
+ at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
+
+ /* Turn off chip select to DataFlash */
+ at91_pio_gpio_output(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11, 0);
+ at91_pio_gpio_set(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11);
+ at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11);
+
+ /* Multimedia Card */
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA0_MCDB0, 1);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA1_MCCDB, 1);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA3_MCDB3, 1);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA4_MCDB2, 1);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA5_MCDB1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA8_MCCK, 1);
+ at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC9);
+#else
+ /* SPI0 to DataFlash */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA2, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC11,0);
+
+ at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8);
+ at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8);
+#endif
+
+ /* EMAC */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA14_ERX0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA15_ERX1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA16_ETXEN, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA17_ERXDV, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA18_ERXER, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA19_ETXCK, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA20_EMDC, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA21_EMDIO, 0);
+
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA10_ETX2_0, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA11_ETX3_0, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA22_ETXER, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA25_ERX2, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA26_ERX3, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA27_ERXCK, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA28_ECRS, 0);
+ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA29_ECOL, 0);
+#endif
+ return (at91_ramsize());
+}
Added: head/sys/arm/at91/std.sam9x25ek
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/std.sam9x25ek Fri Jun 29 04:18:52 2012
(r237742)
@@ -0,0 +1,12 @@
+#$FreeBSD$
+include "../at91/std.at91sam9"
+
+options STARTUP_PAGETABLE_ADDR=0x20800000
+makeoptions KERNPHYSADDR=0x20000000
+makeoptions KERNVIRTADDR=0xc0000000
+options KERNPHYSADDR=0x20000000
+options KERNVIRTADDR=0xc0000000
+
+device at91_board_sam9x25ek
+nodevice at91sam9g20
+nodevice at91sam9260
Added: head/sys/arm/conf/SAM9X25EK
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/SAM9X25EK Fri Jun 29 04:18:52 2012 (r237742)
@@ -0,0 +1,154 @@
+# Kernel configuration for Atmel AT91SAM9G20EK Rev B. development card
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+#
http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+# NOUNIVERSE: disable building in make universe
+ident SAM9X25EK
+
+include "../at91/std.sam9x25ek"
+
+#To statically compile in device wiring instead of /boot/device.hints
+hints "SAM9G20EK.hints"
+makeoptions MODULES_OVERRIDE=""
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+#options INET6 #IPv6 communications protocols
+options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+#options MD_ROOT #MD is a potential root device
+#options MD_ROOT_SIZE=4096 # 3MB ram disk
+options NFSCL #New Network Filesystem Client
+#options NFSD #New Network Filesystem Server
+#options NFSLOCKD #Network Lock Manager
+#options NFS_ROOT #NFS usable as /, requires NFSCL
+#options BOOTP_NFSROOT
+#options BOOTP
+#options BOOTP_NFSV3
+#options BOOTP_WIRED_TO=ate0
+#options BOOTP_COMPAT
+
+options ROOTDEVNAME=\"ufs:/dev/mmcsd0s1a\"
+
+options ALT_BREAK_TO_DEBUGGER
+
+#options MSDOSFS #MSDOS Filesystem
+#options CD9660 #ISO 9660 Filesystem
+#options PROCFS #Process filesystem (requires PSEUDOFS)
+#options PSEUDOFS #Pseudo-filesystem framework
+#options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI
+#options KTRACE #ktrace(1) support
+options SYSVSHM #SYSV-style shared memory
+options SYSVMSG #SYSV-style message queues
+options SYSVSEM #SYSV-style semaphores
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+#options SYSCTL_OMIT_DESCR
+options MUTEX_NOINLINE
+options RWLOCK_NOINLINE
+options NO_FFS_SNAPSHOT
+options NO_SWAPPING
+
+# Debugging for use in -current
+#options INVARIANTS #Enable calls of extra sanity checking
+#options INVARIANT_SUPPORT #Extra sanity checks of internal
structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and
cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for
speed
+#options DIAGNOSTIC
+
+device random
+device pty
+device loop
+device bpf
+device ether
+device md
+
+device uart # Serial Ports
+
+# Ethernet
+#device ate # Ethernet Driver
+device macb # Alternate Ethernet driver
+device mii
+option AT91_ATE_USE_RMII
+
+#device at91_twi # TWI: Two Wire Interface
(EEPROM)
+device at91_wdt # WDT: Watchdog timer
+
+# NOTE: SPI DataFlash and mci/mmc/mmcsd have hardware
+# confilict on this card. Use one or the other.
+# see board_sam9g20ek.c
+
+# SPI: Data Flash
+#device at91_spi # SPI:
+#device spibus
+#device at45d # at45db642 and maybe others
+
+# MMC/SD
+device at91_mci
+device mmc
+device mmcsd
+#option AT91_MCI_SLOT_B
+option AT91_MCI_HAS_4WIRE
+
+# iic
+device iic
+device iicbus
+device icee
+
+# SCSI peripherals
+device scbus # SCSI bus (required for SCSI)
+device da # Direct Access (disks)
+device cd # CD
+device pass # Passthrough device (direct SCSI access)
+
+# USB support
+#device ohci # OHCI localbus->USB interface
+#device usb # USB Bus (required)
+#device umass # Disks/Mass storage - Requires scbus
and da
+#device uhid # "Human Interface Devices"
+#device ulpt # Printer
+#device udbp # USB Double Bulk Pipe devices
+
+# USB Ethernet, requires miibus
+device miibus
+#device aue # ADMtek USB Ethernet
+#device axe # ASIX Electronics USB Ethernet
+#device cdce # Generic USB over Ethernet
+#device cue # CATC USB Ethernet
+#device kue # Kawasaki LSI USB Ethernet
+#device rue # RealTek RTL8150 USB Ethernet
+#device udav # Davicom DM9601E USB
+
+# USB Wireless
+#device rum # Ralink Technology RT2501USB wireless
NICs
+#device uath # Atheros AR5523 wireless NICs
+#device ural # Ralink Technology RT2500USB wireless
NICs
+#device zyd # ZyDAS zd1211/zd1211b wireless NICs
+
+# Wireless NIC cards
+#device wlan # 802.11 support
+#device wlan_wep # 802.11 WEP support
+#device wlan_ccmp # 802.11 CCMP support
+#device wlan_tkip # 802.11 TKIP support
+#device wlan_amrr # AMRR transmit rate control algorithm
+
Added: head/sys/arm/conf/SAM9X25EK.hints
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/SAM9X25EK.hints Fri Jun 29 04:18:52 2012
(r237742)
@@ -0,0 +1,10 @@
+# $FreeBSD$
+#
+
+# EEPROM
+hint.icee.0.at="iicbus0"
+hint.icee.0.addr=0xa0
+hint.icee.0.type=16
+hint.icee.0.size=65536
+hint.icee.0.rd_sz=256
+hint.icee.0.wr_sz=256
_______________________________________________
svn-src-all@freebsd.org mailing list
http://lists.freebsd.org/mailman/listinfo/svn-src-all
To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
