Author: adrian
Date: Sun Jun 17 05:34:41 2012
New Revision: 237183
URL: http://svn.freebsd.org/changeset/base/237183
Log:
Add an disabled workaround for the AR9285SE.
This just requires a little HAL change (add a new config parameter) and
some glue in if_ath_pci.c, however I'm leaving this up for someone else
to do.
Obtained from: Qualcomm Atheros
Modified:
head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Sun Jun 17 04:48:47
2012 (r237182)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Sun Jun 17 05:34:41
2012 (r237183)
@@ -369,6 +369,25 @@ ar9285ConfigPCIE(struct ath_hal *ah, HAL
{
uint32_t val;
+ /*
+ * This workaround needs some integration work with the HAL
+ * config parameters and the if_ath_pci.c glue.
+ * Specifically, read the value of the PCI register 0x70c
+ * (4 byte PCI config space register) and store it in ath_hal_war70c.
+ * Then if it's non-zero, the below WAR would override register
+ * 0x570c upon suspend/resume.
+ */
+#if 0
+ if (AR_SREV_9285E_20(ah)) {
+ val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
+ if (val) {
+ val &= 0xffff00ff;
+ val |= 0x6f00;
+ OS_REG_WRITE(ah, 0x570c, val);
+ }
+ }
+#endif
+
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
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