Author: adrian
Date: Tue Dec 13 05:13:51 2011
New Revision: 228450
URL: http://svn.freebsd.org/changeset/base/228450
Log:
Style(9) changes.
Modified:
head/sys/mips/atheros/ar71xx_chip.c
head/sys/mips/atheros/ar724x_chip.c
head/sys/mips/atheros/ar91xx_chip.c
Modified: head/sys/mips/atheros/ar71xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_chip.c Tue Dec 13 00:38:50 2011
(r228449)
+++ head/sys/mips/atheros/ar71xx_chip.c Tue Dec 13 05:13:51 2011
(r228450)
@@ -37,12 +37,12 @@ __FBSDID("$FreeBSD$");
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
-
+
#include <vm/vm.h>
#include <vm/vm_page.h>
-
+
#include <net/ethernet.h>
-
+
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
@@ -50,11 +50,9 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
-
-#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar71xx_chip.h>
-
#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/sentry5/s5reg.h>
@@ -135,7 +133,7 @@ ar71xx_chip_device_stopped(uint32_t mask
uint32_t reg;
reg = ATH_READ_REG(AR71XX_RST_RESET);
- return ((reg & mask) == mask);
+ return ((reg & mask) == mask);
}
/* Speed is either 10, 100 or 1000 */
@@ -144,20 +142,20 @@ ar71xx_chip_set_pll_ge(int unit, int spe
{
uint32_t pll;
- switch(speed) {
- case 10:
- pll = PLL_ETH_INT_CLK_10;
- break;
- case 100:
- pll = PLL_ETH_INT_CLK_100;
- break;
- case 1000:
- pll = PLL_ETH_INT_CLK_1000;
- break;
- default:
- printf("%s%d: invalid speed %d\n",
- __func__, unit, speed);
- return;
+ switch (speed) {
+ case 10:
+ pll = PLL_ETH_INT_CLK_10;
+ break;
+ case 100:
+ pll = PLL_ETH_INT_CLK_100;
+ break;
+ case 1000:
+ pll = PLL_ETH_INT_CLK_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n",
+ __func__, unit, speed);
+ return;
}
switch (unit) {
case 0:
@@ -180,6 +178,7 @@ ar71xx_chip_set_pll_ge(int unit, int spe
static void
ar71xx_chip_ddr_flush_ge(int unit)
{
+
switch (unit) {
case 0:
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
@@ -209,18 +208,24 @@ ar71xx_chip_get_eth_pll(unsigned int mac
static void
ar71xx_chip_init_usb_peripheral(void)
{
- ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST |
RST_RESET_USB_PHY);
+
+ ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
+ RST_RESET_USB_HOST | RST_RESET_USB_PHY);
DELAY(1000);
- ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST |
RST_RESET_USB_PHY);
+ ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
+ RST_RESET_USB_HOST | RST_RESET_USB_PHY);
DELAY(1000);
ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
- USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
- USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
+ USB_CTRL_CONFIG_OHCI_DES_SWAP |
+ USB_CTRL_CONFIG_OHCI_BUF_SWAP |
+ USB_CTRL_CONFIG_EHCI_DES_SWAP |
+ USB_CTRL_CONFIG_EHCI_BUF_SWAP);
ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
- (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
+ (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
+ (3 << USB_CTRL_FLADJ_A5_SHIFT));
DELAY(1000);
}
Modified: head/sys/mips/atheros/ar724x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar724x_chip.c Tue Dec 13 00:38:50 2011
(r228449)
+++ head/sys/mips/atheros/ar724x_chip.c Tue Dec 13 05:13:51 2011
(r228450)
@@ -37,12 +37,12 @@ __FBSDID("$FreeBSD$");
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
-
+
#include <vm/vm.h>
#include <vm/vm_page.h>
-
+
#include <net/ethernet.h>
-
+
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
@@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
-
+
#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar724xreg.h>
@@ -71,20 +71,20 @@ ar724x_chip_detect_sys_frequency(void)
uint32_t pll;
uint32_t freq;
uint32_t div;
-
+
pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
-
+
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
freq = div * AR724X_BASE_FREQ;
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
freq *= div;
-
+
u_ar71xx_cpu_freq = freq;
-
+
div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
u_ar71xx_ddr_freq = freq / div;
-
+
div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
}
@@ -125,12 +125,13 @@ ar724x_chip_device_stopped(uint32_t mask
static void
ar724x_chip_set_pll_ge(int unit, int speed)
{
+
switch (unit) {
case 0:
- /* TODO */
+ /* XXX TODO */
break;
case 1:
- /* TODO */
+ /* XXX TODO */
break;
default:
printf("%s: invalid PLL set for arge unit: %d\n",
@@ -142,6 +143,7 @@ ar724x_chip_set_pll_ge(int unit, int spe
static void
ar724x_chip_ddr_flush_ge(int unit)
{
+
switch (unit) {
case 0:
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
@@ -159,14 +161,15 @@ ar724x_chip_ddr_flush_ge(int unit)
static void
ar724x_chip_ddr_flush_ip2(void)
{
+
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
}
-
static uint32_t
ar724x_chip_get_eth_pll(unsigned int mac, int speed)
{
- return 0;
+
+ return 0;
}
static void
@@ -174,42 +177,39 @@ ar724x_chip_init_usb_peripheral(void)
{
switch (ar71xx_soc) {
- case AR71XX_SOC_AR7240:
-
- ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
- AR724X_RESET_USB_HOST);
- DELAY(1000);
-
- ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
- AR724X_RESET_USB_HOST);
- DELAY(1000);
-
- /*
- * WAR for HW bug. Here it adjusts the duration
- * between two SOFS.
- */
- ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
- (3 << USB_CTRL_FLADJ_A0_SHIFT));
+ case AR71XX_SOC_AR7240:
+ ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
+ AR724X_RESET_USB_HOST);
+ DELAY(1000);
+
+ ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
+ AR724X_RESET_USB_HOST);
+ DELAY(1000);
+
+ /*
+ * WAR for HW bug. Here it adjusts the duration
+ * between two SOFS.
+ */
+ ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
+ (3 << USB_CTRL_FLADJ_A0_SHIFT));
- break;
-
- case AR71XX_SOC_AR7241:
- case AR71XX_SOC_AR7242:
+ break;
- ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
- DELAY(100);
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
+ DELAY(100);
- ar71xx_device_start(AR724X_RESET_USB_HOST);
- DELAY(100);
+ ar71xx_device_start(AR724X_RESET_USB_HOST);
+ DELAY(100);
- ar71xx_device_start(AR724X_RESET_USB_PHY);
- DELAY(100);
+ ar71xx_device_start(AR724X_RESET_USB_PHY);
+ DELAY(100);
- break;
+ break;
- default:
- /* fallthrough */
- break;
+ default:
+ break;
}
}
Modified: head/sys/mips/atheros/ar91xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar91xx_chip.c Tue Dec 13 00:38:50 2011
(r228449)
+++ head/sys/mips/atheros/ar91xx_chip.c Tue Dec 13 05:13:51 2011
(r228450)
@@ -37,12 +37,12 @@ __FBSDID("$FreeBSD$");
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
-
+
#include <vm/vm.h>
#include <vm/vm_page.h>
-
+
#include <net/ethernet.h>
-
+
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
@@ -50,11 +50,10 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
-
-#include <mips/atheros/ar71xxreg.h>
-#include <mips/atheros/ar91xxreg.h>
+#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar91xxreg.h>
#include <mips/atheros/ar91xx_chip.h>
#include <mips/sentry5/s5reg.h>
@@ -67,49 +66,48 @@ ar91xx_chip_detect_mem_size(void)
static void
ar91xx_chip_detect_sys_frequency(void)
{
- uint32_t pll;
- uint32_t freq;
- uint32_t div;
-
- pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
-
- div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
- freq = div * AR91XX_BASE_FREQ;
-
- u_ar71xx_cpu_freq = freq;
-
- div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
- u_ar71xx_ddr_freq = freq / div;
-
- div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
- u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+ uint32_t pll;
+ uint32_t freq;
+ uint32_t div;
+
+ pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
+
+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
+ freq = div * AR91XX_BASE_FREQ;
+ u_ar71xx_cpu_freq = freq;
+
+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
+ u_ar71xx_ddr_freq = freq / div;
+
+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
+ u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
}
static void
ar91xx_chip_device_stop(uint32_t mask)
{
- uint32_t reg;
-
- reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
- ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
}
static void
ar91xx_chip_device_start(uint32_t mask)
{
- uint32_t reg;
-
- reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
- ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
}
static int
ar91xx_chip_device_stopped(uint32_t mask)
{
- uint32_t reg;
-
- reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
- return ((reg & mask) == mask);
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ return ((reg & mask) == mask);
}
static void
@@ -118,19 +116,19 @@ ar91xx_chip_set_pll_ge(int unit, int spe
uint32_t pll;
switch(speed) {
- case 10:
- pll = AR91XX_PLL_VAL_10;
- break;
- case 100:
- pll = AR91XX_PLL_VAL_100;
- break;
- case 1000:
- pll = AR91XX_PLL_VAL_1000;
- break;
- default:
- printf("%s%d: invalid speed %d\n",
- __func__, unit, speed);
- return;
+ case 10:
+ pll = AR91XX_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR91XX_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n",
+ __func__, unit, speed);
+ return;
}
switch (unit) {
case 0:
@@ -153,6 +151,7 @@ ar91xx_chip_set_pll_ge(int unit, int spe
static void
ar91xx_chip_ddr_flush_ge(int unit)
{
+
switch (unit) {
case 0:
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
@@ -170,6 +169,7 @@ ar91xx_chip_ddr_flush_ge(int unit)
static void
ar91xx_chip_ddr_flush_ip2(void)
{
+
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
}
@@ -177,12 +177,14 @@ ar91xx_chip_ddr_flush_ip2(void)
static uint32_t
ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
{
- return 0;
+
+ return 0;
}
static void
ar91xx_chip_init_usb_peripheral(void)
{
+
ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
DELAY(100);
@@ -201,14 +203,14 @@ ar91xx_chip_init_usb_peripheral(void)
}
struct ar71xx_cpu_def ar91xx_chip_def = {
- &ar91xx_chip_detect_mem_size,
- &ar91xx_chip_detect_sys_frequency,
- &ar91xx_chip_device_stop,
- &ar91xx_chip_device_start,
- &ar91xx_chip_device_stopped,
- &ar91xx_chip_set_pll_ge,
- &ar91xx_chip_ddr_flush_ge,
- &ar91xx_chip_get_eth_pll,
- &ar91xx_chip_ddr_flush_ip2,
+ &ar91xx_chip_detect_mem_size,
+ &ar91xx_chip_detect_sys_frequency,
+ &ar91xx_chip_device_stop,
+ &ar91xx_chip_device_start,
+ &ar91xx_chip_device_stopped,
+ &ar91xx_chip_set_pll_ge,
+ &ar91xx_chip_ddr_flush_ge,
+ &ar91xx_chip_get_eth_pll,
+ &ar91xx_chip_ddr_flush_ip2,
&ar91xx_chip_init_usb_peripheral,
};
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