Author: jchandra
Date: Wed Sep 1 17:35:31 2010
New Revision: 212102
URL: http://svn.freebsd.org/changeset/base/212102
Log:
Updates for the RMI MIPS platform code
- set cache_coherent_dma flag in cpuinfo for XLR, this will make sure that
BUS_DMA_COHERENT flag is handled correctly in busdma_machdep.c
- iodi.c, call device_get_name() just once
- clear RMI specific EIRR while intializing CPUs
- remove debug print in intr_machdep.c
Modified:
head/sys/mips/rmi/intr_machdep.c
head/sys/mips/rmi/iodi.c
head/sys/mips/rmi/pic.h
head/sys/mips/rmi/xlr_machdep.c
Modified: head/sys/mips/rmi/intr_machdep.c
==============================================================================
--- head/sys/mips/rmi/intr_machdep.c Wed Sep 1 17:02:31 2010
(r212101)
+++ head/sys/mips/rmi/intr_machdep.c Wed Sep 1 17:35:31 2010
(r212102)
@@ -62,8 +62,10 @@ static int intrcnt_index;
void
xlr_enable_irq(int irq)
{
+ uint64_t eimr;
- write_c0_eimr64(read_c0_eimr64() | (1ULL << irq));
+ eimr = read_c0_eimr64();
+ write_c0_eimr64(eimr | (1ULL << irq));
}
void
@@ -128,9 +130,6 @@ xlr_establish_intr(const char *name, dri
* FIXME locking - not needed now, because we do this only on
* startup from CPU0
*/
- printf("[%s] Setup intr %d called on cpu %d (%d)\n", name, irq,
- xlr_cpu_id(), PCPU_GET(cpuid));
-
src = &xlr_interrupts[irq];
ie = src->ie;
if (ie == NULL) {
Modified: head/sys/mips/rmi/iodi.c
==============================================================================
--- head/sys/mips/rmi/iodi.c Wed Sep 1 17:02:31 2010 (r212101)
+++ head/sys/mips/rmi/iodi.c Wed Sep 1 17:35:31 2010 (r212102)
@@ -95,7 +95,7 @@ bridge_pcmcia_ack(int irq)
static int
iodi_setup_intr(device_t dev, device_t child,
- struct resource *ires, int flags, driver_filter_t * filt,
+ struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
const char *name = device_get_name(child);
@@ -130,6 +130,7 @@ iodi_alloc_resource(device_t bus, device
u_long start, u_long end, u_long count, u_int flags)
{
struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
+ const char *name = device_get_name(child);
int unit;
#ifdef DEBUG
@@ -151,7 +152,7 @@ iodi_alloc_resource(device_t bus, device
}
#endif
- if (strcmp(device_get_name(child), "uart") == 0) {
+ if (strcmp(name, "uart") == 0) {
if ((unit = device_get_unit(child)) == 0) { /* uart 0 */
res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET);
} else if (unit == 1) {
@@ -160,13 +161,13 @@ iodi_alloc_resource(device_t bus, device
printf("%s: Unknown uart unit\n", __FUNCTION__);
res->r_bustag = uart_bus_space_mem;
- } else if (strcmp(device_get_name(child), "ehci") == 0) {
+ } else if (strcmp(name, "ehci") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000);
res->r_bustag = rmi_pci_bus_space;
- } else if (strcmp(device_get_name(child), "cfi") == 0) {
+ } else if (strcmp(name, "cfi") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000);
res->r_bustag = 0;
- } else if (strcmp(device_get_name(child), "ata") == 0) {
+ } else if (strcmp(name, "ata") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000);
res->r_bustag = rmi_pci_bus_space; /* byte swapping (not
really PCI) */
}
Modified: head/sys/mips/rmi/pic.h
==============================================================================
--- head/sys/mips/rmi/pic.h Wed Sep 1 17:02:31 2010 (r212101)
+++ head/sys/mips/rmi/pic.h Wed Sep 1 17:35:31 2010 (r212102)
@@ -189,7 +189,7 @@ pic_ack(int picintr)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
- xlr_write_reg(mmio, PIC_INT_ACK, 1 << picintr);
+ xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
}
static __inline
Modified: head/sys/mips/rmi/xlr_machdep.c
==============================================================================
--- head/sys/mips/rmi/xlr_machdep.c Wed Sep 1 17:02:31 2010
(r212101)
+++ head/sys/mips/rmi/xlr_machdep.c Wed Sep 1 17:35:31 2010
(r212102)
@@ -266,6 +266,7 @@ mips_init(void)
init_param2(physmem);
mips_cpu_init();
+ cpuinfo.cache_coherent_dma = TRUE;
pmap_bootstrap();
#ifdef DDB
kdb_init();
@@ -298,6 +299,7 @@ xlr_pic_init(void)
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int i, level, irq;
+ write_c0_eimr64(0ULL);
mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
xlr_write_reg(mmio, PIC_CTRL, 0);
@@ -574,6 +576,7 @@ platform_init_ap(int cpuid)
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
mips_wr_status(stat);
+ write_c0_eimr64(0ULL);
xlr_enable_irq(IRQ_IPI);
xlr_enable_irq(IRQ_TIMER);
if (xlr_thr_id() == 0) {
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