Author: jhb Date: Fri Mar 26 13:01:30 2010 New Revision: 205687 URL: http://svn.freebsd.org/changeset/base/205687
Log: MFC 205210,205448: Remove unneeded type specifiers from 64-bit constants. The compiler infers their natural type from the constants' values. Modified: stable/8/sys/amd64/include/specialreg.h stable/8/sys/i386/include/specialreg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) stable/8/sys/net/ (props changed) stable/8/sys/netinet/ipfw/ (props changed) Modified: stable/8/sys/amd64/include/specialreg.h ============================================================================== --- stable/8/sys/amd64/include/specialreg.h Fri Mar 26 12:59:15 2010 (r205686) +++ stable/8/sys/amd64/include/specialreg.h Fri Mar 26 13:01:30 2010 (r205687) @@ -320,16 +320,16 @@ #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 -#define MTRR_CAP_WC 0x0000000000000400UL -#define MTRR_CAP_FIXED 0x0000000000000100UL -#define MTRR_CAP_VCNT 0x00000000000000ffUL -#define MTRR_DEF_ENABLE 0x0000000000000800UL -#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL -#define MTRR_DEF_TYPE 0x00000000000000ffUL -#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL -#define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL -#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL -#define MTRR_PHYSMASK_VALID 0x0000000000000800UL +#define MTRR_CAP_WC 0x0000000000000400 +#define MTRR_CAP_FIXED 0x0000000000000100 +#define MTRR_CAP_VCNT 0x00000000000000ff +#define MTRR_DEF_ENABLE 0x0000000000000800 +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 +#define MTRR_DEF_TYPE 0x00000000000000ff +#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 +#define MTRR_PHYSBASE_TYPE 0x00000000000000ff +#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 +#define MTRR_PHYSMASK_VALID 0x0000000000000800 /* Performance Control Register (5x86 only). */ #define PCR0 0x20 @@ -357,22 +357,22 @@ #define MCG_STATUS_RIPV 0x00000001 #define MCG_STATUS_EIPV 0x00000002 #define MCG_STATUS_MCIP 0x00000004 -#define MCG_CTL_ENABLE 0xffffffffffffffffUL -#define MCG_CTL_DISABLE 0x0000000000000000UL +#define MCG_CTL_ENABLE 0xffffffffffffffff +#define MCG_CTL_DISABLE 0x0000000000000000 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) -#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL -#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL -#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL -#define MC_STATUS_PCC 0x0200000000000000UL -#define MC_STATUS_ADDRV 0x0400000000000000UL -#define MC_STATUS_MISCV 0x0800000000000000UL -#define MC_STATUS_EN 0x1000000000000000UL -#define MC_STATUS_UC 0x2000000000000000UL -#define MC_STATUS_OVER 0x4000000000000000UL -#define MC_STATUS_VAL 0x8000000000000000UL +#define MC_STATUS_MCA_ERROR 0x000000000000ffff +#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 +#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 +#define MC_STATUS_PCC 0x0200000000000000 +#define MC_STATUS_ADDRV 0x0400000000000000 +#define MC_STATUS_MISCV 0x0800000000000000 +#define MC_STATUS_EN 0x1000000000000000 +#define MC_STATUS_UC 0x2000000000000000 +#define MC_STATUS_OVER 0x4000000000000000 +#define MC_STATUS_VAL 0x8000000000000000 /* * The following four 3-byte registers control the non-cacheable regions. Modified: stable/8/sys/i386/include/specialreg.h ============================================================================== --- stable/8/sys/i386/include/specialreg.h Fri Mar 26 12:59:15 2010 (r205686) +++ stable/8/sys/i386/include/specialreg.h Fri Mar 26 13:01:30 2010 (r205687) @@ -326,16 +326,16 @@ #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 -#define MTRR_CAP_WC 0x0000000000000400ULL -#define MTRR_CAP_FIXED 0x0000000000000100ULL -#define MTRR_CAP_VCNT 0x00000000000000ffULL -#define MTRR_DEF_ENABLE 0x0000000000000800ULL -#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL -#define MTRR_DEF_TYPE 0x00000000000000ffULL -#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL -#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL -#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL -#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL +#define MTRR_CAP_WC 0x0000000000000400 +#define MTRR_CAP_FIXED 0x0000000000000100 +#define MTRR_CAP_VCNT 0x00000000000000ff +#define MTRR_DEF_ENABLE 0x0000000000000800 +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 +#define MTRR_DEF_TYPE 0x00000000000000ff +#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 +#define MTRR_PHYSBASE_TYPE 0x00000000000000ff +#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 +#define MTRR_PHYSMASK_VALID 0x0000000000000800 /* * Cyrix configuration registers, accessible as IO ports. @@ -426,22 +426,22 @@ #define MCG_STATUS_RIPV 0x00000001 #define MCG_STATUS_EIPV 0x00000002 #define MCG_STATUS_MCIP 0x00000004 -#define MCG_CTL_ENABLE 0xffffffffffffffffUL -#define MCG_CTL_DISABLE 0x0000000000000000UL +#define MCG_CTL_ENABLE 0xffffffffffffffff +#define MCG_CTL_DISABLE 0x0000000000000000 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) -#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL -#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL -#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL -#define MC_STATUS_PCC 0x0200000000000000UL -#define MC_STATUS_ADDRV 0x0400000000000000UL -#define MC_STATUS_MISCV 0x0800000000000000UL -#define MC_STATUS_EN 0x1000000000000000UL -#define MC_STATUS_UC 0x2000000000000000UL -#define MC_STATUS_OVER 0x4000000000000000UL -#define MC_STATUS_VAL 0x8000000000000000UL +#define MC_STATUS_MCA_ERROR 0x000000000000ffff +#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 +#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 +#define MC_STATUS_PCC 0x0200000000000000 +#define MC_STATUS_ADDRV 0x0400000000000000 +#define MC_STATUS_MISCV 0x0800000000000000 +#define MC_STATUS_EN 0x1000000000000000 +#define MC_STATUS_UC 0x2000000000000000 +#define MC_STATUS_OVER 0x4000000000000000 +#define MC_STATUS_VAL 0x8000000000000000 /* * The following four 3-byte registers control the non-cacheable regions. _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
