Author: gonzo Date: Fri Aug 28 20:25:03 2020 New Revision: 364938 URL: https://svnweb.freebsd.org/changeset/base/364938
Log: MFC r357250, r363926-r363927 r357250 (by ganbold@): Add USB3 related clock definitions for Rockchip RK3328 SoC. Reviewed by: manu r363926: Add flag for SYSCON-controlled clocks on Rockhip platform Ethernet clocks on RK3328 are controlled by SYSCON registers, so add RK_CLK_COMPOSITE_GRF flag to indicate that clock node should access grf registers instead of CRU's Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25918 r363927: Add clocks for ethernet controllers on RK3328 Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25918 Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Fri Aug 28 20:05:18 2020 (r364937) +++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Fri Aug 28 20:25:03 2020 (r364938) @@ -50,8 +50,31 @@ __FBSDID("$FreeBSD$"); #include <arm64/rockchip/clk/rk_cru.h> +/* Registers */ +#define RK3328_GRF_SOC_CON4 0x410 +#define RK3328_GRF_MAC_CON1 0x904 +#define RK3328_GRF_MAC_CON2 0x908 + /* GATES */ +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_USB3OTG_REF 96 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 +#define ACLK_USB3OTG 132 +#define ACLK_GMAC 146 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 #define ACLK_PERI 153 #define PCLK_GPIO0 200 #define PCLK_GPIO1 201 @@ -62,6 +85,12 @@ __FBSDID("$FreeBSD$"); #define PCLK_I2C2 207 #define PCLK_I2C3 208 #define PCLK_TSADC 213 +#define PCLK_GMAC 220 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 #define HCLK_SDMMC 317 #define HCLK_SDIO 318 #define HCLK_EMMC 319 @@ -77,11 +106,20 @@ static struct rk_cru_gate rk3328_gates[] = { /* CRU_CLKGATE_CON4 */ CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0) CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1) + CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0x210, 7) /* CRU_CLKGATE_CON8 */ CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3) CRU_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4) + /* CRU_CLKGATE_CON8 */ + CRU_GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7) + CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6) + CRU_GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5) + CRU_GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4) + CRU_GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0x224, 3) + CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0x224, 1) + /* CRU_CLKGATE_CON10 */ CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) @@ -99,13 +137,27 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10) + /* CRU_CLKGATE_CON17 */ + CRU_GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", 0x244, 2) + /* CRU_CLKGATE_CON19 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1) CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2) CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12) CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13) + CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14) CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) + + /* CRU_CLKGATE_CON26 */ + CRU_GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0x268, 0) + CRU_GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0x268, 1) + CRU_GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2) + CRU_GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3) + + /* CRU_CLKGATE_CON28 */ + CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0x270, 1) + CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0x270, 2) }; /* @@ -992,6 +1044,282 @@ static struct rk_clk_composite_def i2c3 = { .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 + +static const char *ref_usb3otg_parents[] = { "xin24m", "clk_usb3otg_ref" }; + +static struct rk_clk_composite_def ref_usb3otg = { + .clkdef = { + .id = SCLK_REF_USB3OTG, + .name = "clk_ref_usb3otg", + .parent_names = ref_usb3otg_parents, + .parent_cnt = nitems(ref_usb3otg_parents), + }, + .muxdiv_offset = 0x1B4, + + .mux_shift = 8, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *usb3otg_suspend_parents[] = { "xin24m"/*, "clk_rtc32k" */}; + +static struct rk_clk_composite_def usb3otg_suspend = { + .clkdef = { + .id = SCLK_USB3OTG_SUSPEND, + .name = "clk_usb3otg_suspend", + .parent_names = usb3otg_suspend_parents, + .parent_cnt = nitems(usb3otg_suspend_parents), + }, + .muxdiv_offset = 0x184, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 0, + .div_width = 10, + + /* CRU_CLKGATE_CON4 */ + .gate_offset = 0x210, + .gate_shift = 8, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *ref_usb3otg_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def ref_usb3otg_src = { + .clkdef = { + .id = SCLK_REF_USB3OTG_SRC, + .name = "clk_ref_usb3otg_src", + .parent_names = ref_usb3otg_src_parents, + .parent_cnt = nitems(ref_usb3otg_src_parents), + }, + .muxdiv_offset = 0x1B4, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON4 */ + .gate_offset = 0x210, + .gate_shift = 9, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *mac2io_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2io_src = { + .clkdef = { + .id = SCLK_MAC2IO_SRC, + .name = "clk_mac2io_src", + .parent_names = mac2io_src_parents, + .parent_cnt = nitems(mac2io_src_parents), + }, + /* CRU_CLKSEL_CON27 */ + .muxdiv_offset = 0x16c, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2io_out_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2io_out = { + .clkdef = { + .id = SCLK_MAC2IO_OUT, + .name = "clk_mac2io_out", + .parent_names = mac2io_out_parents, + .parent_cnt = nitems(mac2io_out_parents), + }, + /* CRU_CLKSEL_CON27 */ + .muxdiv_offset = 0x16c, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2io_parents[] = { "clk_mac2io_src", "gmac_clkin" }; + +static struct rk_clk_composite_def mac2io = { + .clkdef = { + .id = SCLK_MAC2IO, + .name = "clk_mac2io", + .parent_names = mac2io_parents, + .parent_cnt = nitems(mac2io_parents), + }, + .muxdiv_offset = RK3328_GRF_MAC_CON1, + + .mux_shift = 10, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; + +static struct rk_clk_composite_def mac2io_ext = { + .clkdef = { + .id = SCLK_MAC2IO_EXT, + .name = "clk_mac2io_ext", + .parent_names = mac2io_ext_parents, + .parent_cnt = nitems(mac2io_ext_parents), + }, + .muxdiv_offset = RK3328_GRF_SOC_CON4, + + .mux_shift = 14, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2phy_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2phy_src = { + .clkdef = { + .id = SCLK_MAC2PHY_SRC, + .name = "clk_mac2phy_src", + .parent_names = mac2phy_src_parents, + .parent_cnt = nitems(mac2phy_src_parents), + }, + /* CRU_CLKSEL_CON26 */ + .muxdiv_offset = 0x168, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2phy_parents[] = { "clk_mac2phy_src", "phy_50m_out" }; + +static struct rk_clk_composite_def mac2phy = { + .clkdef = { + .id = SCLK_MAC2PHY, + .name = "clk_mac2phy", + .parent_names = mac2phy_parents, + .parent_cnt = nitems(mac2phy_parents), + }, + .muxdiv_offset = RK3328_GRF_MAC_CON2, + + .mux_shift = 10, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2phy_out_parents[] = { "clk_mac2phy" }; + +static struct rk_clk_composite_def mac2phy_out = { + .clkdef = { + .id = SCLK_MAC2PHY_OUT, + .name = "clk_mac2phy_out", + .parent_names = mac2phy_out_parents, + .parent_cnt = nitems(mac2phy_out_parents), + }, + /* CRU_CLKSEL_CON26 */ + .muxdiv_offset = 0x168, + + .div_shift = 8, + .div_width = 2, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x224, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE +}; + +static struct clk_fixed_def phy_50m_out = { + .clkdef.name = "phy_50m_out", + .freq = 50000000, +}; + +static struct clk_link_def gmac_clkin = { + .clkdef.name = "gmac_clkin", +}; + +static const char *aclk_gmac_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def aclk_gmac = { + .clkdef = { + .id = ACLK_GMAC, + .name = "aclk_gmac", + .parent_names = aclk_gmac_parents, + .parent_cnt = nitems(aclk_gmac_parents), + }, + /* CRU_CLKSEL_CON35 */ + .muxdiv_offset = 0x18c, + + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *pclk_gmac_parents[] = { "aclk_gmac" }; + +static struct rk_clk_composite_def pclk_gmac = { + .clkdef = { + .id = PCLK_GMAC, + .name = "pclk_gmac", + .parent_names = pclk_gmac_parents, + .parent_cnt = nitems(pclk_gmac_parents), + }, + /* CRU_CLKSEL_CON25 */ + .muxdiv_offset = 0x164, + + .div_shift = 8, + .div_width = 3, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x224, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE +}; + static struct rk_clk rk3328_clks[] = { { .type = RK3328_CLK_PLL, @@ -1076,6 +1404,63 @@ static struct rk_clk rk3328_clks[] = { { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c3 + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &ref_usb3otg + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &ref_usb3otg_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &usb3otg_suspend + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_out + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_ext + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy_out + }, + { + .type = RK_CLK_FIXED, + .clk.fixed = &phy_50m_out + }, + { + .type = RK_CLK_LINK, + .clk.link = &gmac_clkin + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_gmac + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_gmac }, }; Modified: stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c Fri Aug 28 20:05:18 2020 (r364937) +++ stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c Fri Aug 28 20:25:03 2020 (r364938) @@ -36,10 +36,12 @@ __FBSDID("$FreeBSD$"); #include <sys/bus.h> #include <dev/extres/clk/clk.h> +#include <dev/extres/syscon/syscon.h> #include <arm64/rockchip/clk/rk_clk_composite.h> #include "clkdev_if.h" +#include "syscon_if.h" struct rk_clk_composite_sc { uint32_t muxdiv_offset; @@ -55,12 +57,14 @@ struct rk_clk_composite_sc { uint32_t gate_shift; uint32_t flags; + + struct syscon *grf; }; #define WRITE4(_clk, off, val) \ - CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) + rk_clk_composite_write_4(_clk, off, val) #define READ4(_clk, off, val) \ - CLKDEV_READ_4(clknode_get_device(_clk), off, val) + rk_clk_composite_read_4(_clk, off, val) #define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ @@ -75,6 +79,49 @@ struct rk_clk_composite_sc { #define dprintf(format, arg...) #endif +static void +rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + *val = SYSCON_READ_4(sc->grf, addr); + else + CLKDEV_READ_4(clknode_get_device(clk), addr, val); +} + +static void +rk_clk_composite_write_4(struct clknode *clk, bus_addr_t addr, uint32_t val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + SYSCON_WRITE_4(sc->grf, addr, val | (0xffff << 16)); + else + CLKDEV_WRITE_4(clknode_get_device(clk), addr, val); +} + +static struct syscon * +rk_clk_composite_get_grf(struct clknode *clk) +{ + device_t dev; + phandle_t node; + struct syscon *grf; + + grf = NULL; + dev = clknode_get_device(clk); + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &grf) != 0) { + return (NULL); + } + + return (grf); +} + static int rk_clk_composite_init(struct clknode *clk, device_t dev) { @@ -82,6 +129,12 @@ rk_clk_composite_init(struct clknode *clk, device_t de uint32_t val, idx; sc = clknode_get_softc(clk); + if ((sc->flags & RK_CLK_COMPOSITE_GRF) != 0) { + sc->grf = rk_clk_composite_get_grf(clk); + if (sc->grf == NULL) + panic("clock %s has GRF flag set but no syscon is available", + clknode_get_name(clk)); + } idx = 0; if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) != 0) { Modified: stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h Fri Aug 28 20:05:18 2020 (r364937) +++ stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h Fri Aug 28 20:25:03 2020 (r364938) @@ -54,6 +54,7 @@ struct rk_clk_composite_def { #define RK_CLK_COMPOSITE_HAVE_GATE 0x0002 #define RK_CLK_COMPOSITE_DIV_EXP 0x0004 /* Register 0, 1, 2, 2, ... */ /* Divider 1, 2, 4, 8, ... */ +#define RK_CLK_COMPOSITE_GRF 0x0008 /* Use syscon registers instead of CRU's */ int rk_clk_composite_register(struct clkdom *clkdom, struct rk_clk_composite_def *clkdef); _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
