Author: kib
Date: Fri Jun 19 13:46:06 2020
New Revision: 362380
URL: https://svnweb.freebsd.org/changeset/base/362380

Log:
  MFC r340716 (by bwidawsk):
  Add definitions for Intel Speed Shift.

Modified:
  stable/11/sys/x86/include/specialreg.h
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/sys/x86/include/specialreg.h
==============================================================================
--- stable/11/sys/x86/include/specialreg.h      Fri Jun 19 13:09:00 2020        
(r362379)
+++ stable/11/sys/x86/include/specialreg.h      Fri Jun 19 13:46:06 2020        
(r362380)
@@ -187,6 +187,12 @@
 #define        CPUTPM1_SENSOR  0x00000001
 #define        CPUTPM1_TURBO   0x00000002
 #define        CPUTPM1_ARAT    0x00000004
+#define        CPUTPM1_HWP     0x00000080
+#define        CPUTPM1_HWP_NOTIFICATION        0x00000100
+#define        CPUTPM1_HWP_ACTIVITY_WINDOW     0x00000200
+#define        CPUTPM1_HWP_PERF_PREF   0x00000400
+#define        CPUTPM1_HWP_PKG 0x00000800
+#define        CPUTPM1_HWP_FLEXIBLE    0x00020000
 #define        CPUTPM2_EFFREQ  0x00000001
 
 /*
@@ -519,7 +525,14 @@
 #define        MSR_DRAM_ENERGY_STATUS  0x619
 #define        MSR_PP0_ENERGY_STATUS   0x639
 #define        MSR_PP1_ENERGY_STATUS   0x641
+#define        MSR_PPERF               0x64e
 #define        MSR_TSC_DEADLINE        0x6e0   /* Writes are not serializing */
+#define        MSR_IA32_PM_ENABLE      0x770
+#define        MSR_IA32_HWP_CAPABILITIES       0x771
+#define        MSR_IA32_HWP_REQUEST_PKG        0x772
+#define        MSR_IA32_HWP_INTERRUPT          0x773
+#define        MSR_IA32_HWP_REQUEST    0x774
+#define        MSR_IA32_HWP_STATUS     0x777
 
 /*
  * VMX MSRs
@@ -616,6 +629,25 @@
 
 /* MSR IA32_FLUSH_CMD */
 #define        IA32_FLUSH_CMD_L1D      0x00000001
+
+/* MSR IA32_HWP_CAPABILITIES */
+#define        IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x)    (((x) >> 0) & 
0xff)
+#define        IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 
0xff)
+#define        IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x)  (((x) >> 16) & 
0xff)
+#define        IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x)     (((x) >> 24) & 
0xff)
+
+/* MSR IA32_HWP_REQUEST */
+#define        IA32_HWP_REQUEST_MINIMUM_VALID                  (1ULL << 63)
+#define        IA32_HWP_REQUEST_MAXIMUM_VALID                  (1ULL << 62)
+#define        IA32_HWP_REQUEST_DESIRED_VALID                  (1ULL << 61)
+#define        IA32_HWP_REQUEST_EPP_VALID                      (1ULL << 60)
+#define        IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID          (1ULL << 59)
+#define        IA32_HWP_REQUEST_PACKAGE_CONTROL                (1ULL << 42)
+#define        IA32_HWP_ACTIVITY_WINDOW                        (0x3ffULL << 32)
+#define        IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE  (0xffULL << 24)
+#define        IA32_HWP_DESIRED_PERFORMANCE                    (0xffULL << 16)
+#define        IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE            (0xffULL << 8)
+#define        IA32_HWP_MINIMUM_PERFORMANCE                    (0xffULL << 0)
 
 /*
  * PAT modes.
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