Author: manu
Date: Wed Mar 4 21:12:08 2020
New Revision: 358647
URL: https://svnweb.freebsd.org/changeset/base/358647
Log:
MFC r355624, r355852-r355853
r355624:
arm64: rk3328: Add the *clk_peri_niu clocks
Those clocks are always enable by default and are not really explained
in the TRM but the reason we had them is that they have the periph clock
as a parent and those parent should never be disable which can happen
if we disable all the childs. The current childs are the sd/emmc/sdio clocks
so the board will hang if we disable them.
r355852:
arm64: rockchip: rk_pinctrl: Fix clear bits in SYSCON_MODIFY
r351187 change the SYSCON_WRITE to SYSCON_MODIFY but didn't changed the
mask variable that used to hold the bitmask in the upper 16 bits of the
register that control which bits are changed. So we ended up clearing
bit from the upper 16bits half which are always 0 after a read.
Use the correct bit mask for bits that we want to clear.
r355853:
arm64: rockchip: rk_gpio: Fix pin number
The maxpin counter starts at 0, fix one by one error.
This is still not totally correct for some banks in some SoC that have
fewer pins but this will be dealt with in another commit.
Modified:
stable/12/sys/arm64/rockchip/clk/rk3328_cru.c
stable/12/sys/arm64/rockchip/rk_gpio.c
stable/12/sys/arm64/rockchip/rk_pinctrl.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Mar 4 21:06:29
2020 (r358646)
+++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Mar 4 21:12:08
2020 (r358647)
@@ -103,6 +103,8 @@ static struct rk_cru_gate rk3328_gates[] = {
CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0)
CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1)
CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2)
+ CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12)
+ CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13)
CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15)
};
Modified: stable/12/sys/arm64/rockchip/rk_gpio.c
==============================================================================
--- stable/12/sys/arm64/rockchip/rk_gpio.c Wed Mar 4 21:06:29 2020
(r358646)
+++ stable/12/sys/arm64/rockchip/rk_gpio.c Wed Mar 4 21:12:08 2020
(r358647)
@@ -196,7 +196,7 @@ rk_gpio_pin_max(device_t dev, int *maxpin)
{
/* Each bank have always 32 pins */
- *maxpin = 32;
+ *maxpin = 31;
return (0);
}
Modified: stable/12/sys/arm64/rockchip/rk_pinctrl.c
==============================================================================
--- stable/12/sys/arm64/rockchip/rk_pinctrl.c Wed Mar 4 21:06:29 2020
(r358646)
+++ stable/12/sys/arm64/rockchip/rk_pinctrl.c Wed Mar 4 21:12:08 2020
(r358647)
@@ -883,7 +883,7 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc,
reg += bank * 0x10 + ((pin / 8) * 0x4);
bit = (pin % 8) * 2;
- mask = (0x3 << bit) << 16;
+ mask = (0x3 << bit);
SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));
}
@@ -891,7 +891,7 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc,
rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®);
if (rv == 0) {
bit = (pin % 8) * 2;
- mask = (0x3 << bit) << 16;
+ mask = (0x3 << bit);
SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16));
}
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