Author: markj
Date: Mon Sep 23 14:29:05 2019
New Revision: 352625
URL: https://svnweb.freebsd.org/changeset/base/352625
Log:
Revert r316820.
Despite appearing correct, r316820 breaks packet rx/tx for jme(4)
interfaces. With 12.1 approaching, let's just revert the commit for now.
PR: 233952
Tested by: Armin Gruner <ag-free...@muc.de>
MFC after: 3 days
Modified:
head/sys/dev/jme/if_jme.c
Modified: head/sys/dev/jme/if_jme.c
==============================================================================
--- head/sys/dev/jme/if_jme.c Mon Sep 23 14:19:41 2019 (r352624)
+++ head/sys/dev/jme/if_jme.c Mon Sep 23 14:29:05 2019 (r352625)
@@ -559,7 +559,7 @@ jme_map_intr_vector(struct jme_softc *sc)
bzero(map, sizeof(map));
/* Map Tx interrupts source to MSI/MSIX vector 2. */
- map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] |=
+ map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
@@ -581,37 +581,37 @@ jme_map_intr_vector(struct jme_softc *sc)
MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
/* Map Rx interrupts source to MSI/MSIX vector 1. */
- map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
- map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
- map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
- map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
- map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
- map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
- map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
- map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
- map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
- map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
- map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
- map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
- map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
- map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
- map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
- map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] |=
+ map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
/* Map all other interrupts source to MSI/MSIX vector 0. */
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