Author: manu Date: Wed Aug 7 18:35:59 2019 New Revision: 350689 URL: https://svnweb.freebsd.org/changeset/base/350689
Log: MFC r341404-r341405, r344699, r347024, r347442 r341404 by andreast: Add rule to build the dtb for the rock64 board. Reviewed by: manu@ r341405 by andreast: Build the dtb for the rock64 board. Reviewed by: manu@ r344699: arm64: rockchip: rk3399_pll: Fix the recalc function The plls frequency are now correctly calculated in fractional mode and integer mode. While here add some debug printfs (disabled by default) Tested with powerd on the little cluster on a RockPro64. r347024: dtb: Include RK3399 RockPro64 DTS in kernel build The DTS for this board is already present in sys/gnu/dts/arm64/rockchip/ and just needs to be enabled. Submitted by: a...@wied.io Differential Revision: https://reviews.freebsd.org/D19823 r347442: arm64: rockchip: Don't always put PLL to normal mode We used to put every PLL in normal mode (meaning that the output would be the result of the PLL configuration) instead of slow mode (the output is equal to the external oscillator frequency, 24-26Mhz) but this doesn't work for most of the PLLs as when we put them into normal mode the registers configuring the output frequency haven't been set. Add a normal_mode member in clk_pll_def/clk_pll_sc struct and if it's true we then set the PLL to normal mode. For now only set it to the LPLL and BPLL (Little cluster PLL and Big cluster PLL respectively). Reviewed by: ganbold Differential Revision: https://reviews.freebsd.org/D20174 Added: stable/12/sys/modules/dtb/rockchip/ - copied from r341405, head/sys/modules/dtb/rockchip/ Modified: stable/12/sys/arm64/conf/GENERIC stable/12/sys/arm64/rockchip/clk/rk3399_cru.c stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c stable/12/sys/arm64/rockchip/clk/rk_clk_pll.h stable/12/sys/modules/dtb/rockchip/Makefile Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/conf/GENERIC ============================================================================== --- stable/12/sys/arm64/conf/GENERIC Wed Aug 7 18:32:01 2019 (r350688) +++ stable/12/sys/arm64/conf/GENERIC Wed Aug 7 18:35:59 2019 (r350689) @@ -298,4 +298,4 @@ options FDT device acpi # DTBs -makeoptions MODULES_EXTRA="dtb/allwinner dtb/rpi" +makeoptions MODULES_EXTRA="dtb/allwinner dtb/rockchip dtb/rpi" Modified: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Wed Aug 7 18:32:01 2019 (r350688) +++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Wed Aug 7 18:35:59 2019 (r350689) @@ -752,6 +752,7 @@ static struct rk_clk_pll_def lpll = { .gate_shift = 0, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, + .normal_mode = true, }; static struct rk_clk_pll_def bpll = { @@ -766,6 +767,7 @@ static struct rk_clk_pll_def bpll = { .gate_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, + .normal_mode = true, }; static struct rk_clk_pll_def dpll = { Modified: stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c Wed Aug 7 18:32:01 2019 (r350688) +++ stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c Wed Aug 7 18:35:59 2019 (r350689) @@ -54,6 +54,8 @@ struct rk_clk_pll_sc { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; + + bool normal_mode; }; #define WRITE4(_clk, off, val) \ @@ -344,11 +346,13 @@ rk3399_clk_pll_init(struct clknode *clk, device_t dev) sc = clknode_get_softc(clk); - /* Setting to normal mode */ - reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; - reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; - WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, - reg | RK3399_CLK_PLL_WRITE_MASK); + if (sc->normal_mode) { + /* Setting to normal mode */ + reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; + reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, + reg | RK3399_CLK_PLL_WRITE_MASK); + } clknode_init_parent_idx(clk, 0); @@ -359,44 +363,57 @@ static int rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq) { struct rk_clk_pll_sc *sc; - uint64_t rate; uint32_t dsmpd, refdiv, fbdiv; - uint32_t postdiv1, postdiv2, frac; - uint32_t raw1, raw2, raw3, raw4; + uint32_t postdiv1, postdiv2, fracdiv; + uint32_t con1, con2, con3, con4; + uint64_t foutvco; sc = clknode_get_softc(clk); DEVICE_LOCK(clk); - READ4(clk, sc->base_offset, &raw1); - READ4(clk, sc->base_offset + 4, &raw2); - READ4(clk, sc->base_offset + 8, &raw3); - READ4(clk, sc->base_offset + 0xC, &raw4); + READ4(clk, sc->base_offset, &con1); + READ4(clk, sc->base_offset + 4, &con2); + READ4(clk, sc->base_offset + 8, &con3); + READ4(clk, sc->base_offset + 0xC, &con4); DEVICE_UNLOCK(clk); - fbdiv = (raw1 & RK3399_CLK_PLL_FBDIV_MASK) >> RK3399_CLK_PLL_FBDIV_SHIFT; + dprintf("con0: %x\n", con1); + dprintf("con1: %x\n", con2); + dprintf("con2: %x\n", con3); + dprintf("con3: %x\n", con4); - postdiv1 = (raw2 & RK3399_CLK_PLL_POSTDIV1_MASK) >> RK3399_CLK_PLL_POSTDIV1_SHIFT; - postdiv2 = (raw2 & RK3399_CLK_PLL_POSTDIV2_MASK) >> RK3399_CLK_PLL_POSTDIV2_SHIFT; - refdiv = (raw2 & RK3399_CLK_PLL_REFDIV_MASK) >> RK3399_CLK_PLL_REFDIV_SHIFT; + fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK) >> RK3399_CLK_PLL_FBDIV_SHIFT; - frac = (raw3 & RK3399_CLK_PLL_FRAC_MASK) >> RK3399_CLK_PLL_FRAC_SHIFT; + postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) >> RK3399_CLK_PLL_POSTDIV1_SHIFT; + postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK) >> RK3399_CLK_PLL_POSTDIV2_SHIFT; + refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK) >> RK3399_CLK_PLL_REFDIV_SHIFT; - dsmpd = (raw4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT; + fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK) >> RK3399_CLK_PLL_FRAC_SHIFT; + fracdiv >>= 24; - rate = *freq * fbdiv / refdiv; + dsmpd = (con4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT; + + dprintf("fbdiv: %d\n", fbdiv); + dprintf("postdiv1: %d\n", postdiv1); + dprintf("postdiv2: %d\n", postdiv2); + dprintf("refdiv: %d\n", refdiv); + dprintf("fracdiv: %d\n", fracdiv); + dprintf("dsmpd: %d\n", dsmpd); + + dprintf("parent freq=%lu\n", *freq); + if (dsmpd == 0) { /* Fractional mode */ - uint64_t frac_rate; - - frac_rate = *freq * frac / refdiv; - rate += frac_rate >> 24; + foutvco = *freq / refdiv * (fbdiv + fracdiv); + } else { + /* Integer mode */ + foutvco = *freq / refdiv * fbdiv; } + dprintf("foutvco: %lu\n", foutvco); - *freq = rate / postdiv1 / postdiv2; + *freq = foutvco / postdiv1 / postdiv2; + dprintf("freq: %lu\n", *freq); - if (*freq % 2) - *freq = *freq + 1; - return (0); } @@ -508,6 +525,7 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct sc->flags = clkdef->flags; sc->rates = clkdef->rates; sc->frac_rates = clkdef->frac_rates; + sc->normal_mode = clkdef->normal_mode; clknode_register(clkdom, clk); Modified: stable/12/sys/arm64/rockchip/clk/rk_clk_pll.h ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_clk_pll.h Wed Aug 7 18:32:01 2019 (r350688) +++ stable/12/sys/arm64/rockchip/clk/rk_clk_pll.h Wed Aug 7 18:35:59 2019 (r350689) @@ -57,6 +57,8 @@ struct rk_clk_pll_def { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; + + bool normal_mode; }; #define RK_CLK_PLL_HAVE_GATE 0x1 Modified: stable/12/sys/modules/dtb/rockchip/Makefile ============================================================================== --- head/sys/modules/dtb/rockchip/Makefile Sun Dec 2 19:36:20 2018 (r341405) +++ stable/12/sys/modules/dtb/rockchip/Makefile Wed Aug 7 18:35:59 2019 (r350689) @@ -1,7 +1,7 @@ # $FreeBSD$ -# For now only for rk3328-rock64 dts file. DTS= \ - rockchip/rk3328-rock64.dts + rockchip/rk3328-rock64.dts \ + rockchip/rk3399-rockpro64.dts .include <bsd.dtb.mk> _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
