Can you explain why this is necessary? Both functions are run in the
same context and this way of doing things breaks important abstraction
barriers.
Since it also breaks booting on pHyp systems, I would appreciate it if
you could revert this pending review.
-Nathan
On 01/29/18 01:27, Wojciech Macek wrote:
Author: wma
Date: Mon Jan 29 09:27:02 2018
New Revision: 328537
URL: https://svnweb.freebsd.org/changeset/base/328537
Log:
PowerNV: move LPCR and LPID altering to cpudep_ap_early_bootstrap
It turns out that under some circumstances we can get DSI or DSE before we set
LPCR and LPID so we should set it as early as possible.
Authored by: Patryk Duda <p...@semihalf.com>
Submitted by: Wojciech Macek <w...@semihalf.com>
Obtained from: Semihalf
Sponsored by: IBM, QCM Technologies
Modified:
head/sys/powerpc/aim/mp_cpudep.c
head/sys/powerpc/powernv/platform_powernv.c
Modified: head/sys/powerpc/aim/mp_cpudep.c
==============================================================================
--- head/sys/powerpc/aim/mp_cpudep.c Mon Jan 29 09:24:28 2018
(r328536)
+++ head/sys/powerpc/aim/mp_cpudep.c Mon Jan 29 09:27:02 2018
(r328537)
@@ -64,9 +64,6 @@ cpudep_ap_early_bootstrap(void)
register_t reg;
#endif
- __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
- powerpc_sync();
-
switch (mfpvr() >> 16) {
case IBM970:
case IBM970FX:
@@ -86,7 +83,20 @@ cpudep_ap_early_bootstrap(void)
#endif
powerpc_sync();
break;
+ case IBMPOWER8:
+ case IBMPOWER8E:
+ isync();
+ /* Direct interrupts to SRR instead of HSRR and reset LPCR
otherwise */
+ mtspr(SPR_LPID, 0);
+ isync();
+
+ mtspr(SPR_LPCR, LPCR_LPES);
+ isync();
+ break;
}
+
+ __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
+ powerpc_sync();
}
uintptr_t
Modified: head/sys/powerpc/powernv/platform_powernv.c
==============================================================================
--- head/sys/powerpc/powernv/platform_powernv.c Mon Jan 29 09:24:28 2018
(r328536)
+++ head/sys/powerpc/powernv/platform_powernv.c Mon Jan 29 09:27:02 2018
(r328537)
@@ -128,6 +128,7 @@ powernv_attach(platform_t plat)
pcell_t prop;
phandle_t cpu;
int res, len, node, idx;
+ register_t msr;
/* Ping OPAL again just to make sure */
opal_check();
@@ -141,6 +142,19 @@ powernv_attach(platform_t plat)
cpu_idle_hook = powernv_cpu_idle;
powernv_boot_pir = mfspr(SPR_PIR);
+ /* LPID must not be altered when PSL_DR or PSL_IR is set */
+ msr = mfmsr();
+ mtmsr(msr & ~(PSL_DR | PSL_IR));
+
+ /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
+ mtspr(SPR_LPID, 0);
+ isync();
+
+ mtmsr(msr);
+
+ mtspr(SPR_LPCR, LPCR_LPES);
+ isync();
+
/* Init CPU bits */
powernv_smp_ap_init(plat);
@@ -444,21 +458,6 @@ powernv_reset(platform_t platform)
static void
powernv_smp_ap_init(platform_t platform)
{
- register_t msr;
-
- /* LPID must not be altered when PSL_DR or PSL_IR is set */
- msr = mfmsr();
- mtmsr(msr & ~(PSL_DR | PSL_IR));
-
- isync();
- /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
- mtspr(SPR_LPID, 0);
- isync();
-
- mtmsr(msr);
-
- mtspr(SPR_LPCR, LPCR_LPES);
- isync();
}
static void
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