Author: ed
Date: Fri Nov 24 13:51:59 2017
New Revision: 326166
URL: https://svnweb.freebsd.org/changeset/base/326166
Log:
Set CP15BEN in SCTLR to make memory barriers work in 32-bit mode.
Binaries generated by Clang for ARMv6 may contain these instructions:
MCR p15, 0, <Rd>, c7, c10, 5
These instructions are deprecated as of ARMv7, which is why modern
processors have a way of toggling support for them. On FreeBSD/arm64 we
currently disable support for these instructions, meaning that if 32-bit
executables with these instructions are run, they would crash with
SIGILL. This is likely not what we want.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D13145
Modified:
head/sys/arm64/arm64/locore.S
Modified: head/sys/arm64/arm64/locore.S
==============================================================================
--- head/sys/arm64/arm64/locore.S Fri Nov 24 13:50:53 2017
(r326165)
+++ head/sys/arm64/arm64/locore.S Fri Nov 24 13:51:59 2017
(r326166)
@@ -628,11 +628,12 @@ sctlr_set:
/* Bits to set */
.quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
- SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M)
+ SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \
+ SCTLR_M | SCTLR_CP15BEN)
sctlr_clear:
/* Bits to clear */
.quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \
- SCTLR_ITD | SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A)
+ SCTLR_ITD | SCTLR_THEE | SCTLR_A)
.globl abort
abort:
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