On Oct 26, 2009, at 1:11 PM, Marius Strobl wrote:
The cheetah-class CPUs, i.e. USIII and later, take care of I$ coherency themselves, unlike the spitfire ones (see also cheetah_icache_page_inval() vs. spitfire_icache_page_inval()).
This explains why I didn't see any I-cache coherency issues :-)
I currently can't think of any existing code which would ensure I$ consistency after the writes have been performed, not even as a side-effect. The proper solution probalby is to make pmap_sync_icache() a wrapper around icache_page_inval().
I concur. Do we have any spitfire-based sparc64 boxes in the cluster or do you have one? -- Marcel Moolenaar xcl...@mac.com _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
