Author: mmel
Date: Sun Apr 16 06:35:09 2017
New Revision: 317002
URL: https://svnweb.freebsd.org/changeset/base/317002
Log:
MFC r306631,r306640,r306641,r306650,r306656:
r306631:
Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement.
r306640:
Only define the CF_* macros on ARMv4/v5. They are unused on armv6.
r306641:
Remove the parts of cpu_functions from armv6 that are unused on that
architecture.
r306650:
Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit
code so could run a 32-bit kernel.
r306656:
Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs.
This list is incomplete, however we don't have the ID values for the
missing Cortex-A32 or A35.
Modified:
stable/11/sys/arm/arm/cpufunc.c
stable/11/sys/arm/arm/genassym.c
stable/11/sys/arm/include/armreg.h
stable/11/sys/arm/include/cpufunc.h
Directory Properties:
stable/11/ (props changed)
Modified: stable/11/sys/arm/arm/cpufunc.c
==============================================================================
--- stable/11/sys/arm/arm/cpufunc.c Sun Apr 16 06:00:14 2017
(r317001)
+++ stable/11/sys/arm/arm/cpufunc.c Sun Apr 16 06:35:09 2017
(r317002)
@@ -241,50 +241,23 @@ struct cpu_functions sheeva_cpufuncs = {
#ifdef CPU_MV_PJ4B
struct cpu_functions pj4bv7_cpufuncs = {
- /* CPU functions */
-
- armv7_drain_writebuf, /* cpwait */
-
/* MMU functions */
-
- cpufunc_control, /* control */
- armv7_setttb, /* Setttb */
-
- /* TLB functions */
-
- armv7_tlb_flushID, /* tlb_flushID */
- armv7_tlb_flushID_SE, /* tlb_flushID_SE */
- armv7_tlb_flushID, /* tlb_flushD */
- armv7_tlb_flushID_SE, /* tlb_flushD_SE */
+ .cf_control = cpufunc_control,
+ .cf_setttb = armv7_setttb,
/* Cache operations */
- armv7_icache_sync_range, /* icache_sync_range */
-
- armv7_dcache_wbinv_all, /* dcache_wbinv_all */
- armv7_dcache_wbinv_range, /* dcache_wbinv_range */
- armv7_dcache_inv_range, /* dcache_inv_range */
- armv7_dcache_wb_range, /* dcache_wb_range */
-
- armv7_idcache_inv_all, /* idcache_inv_all */
- armv7_idcache_wbinv_all, /* idcache_wbinv_all */
- armv7_idcache_wbinv_range, /* idcache_wbinv_all */
-
- (void *)cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
- (void *)cpufunc_nullop, /* l2cache_drain_writebuf */
+ .cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
+ .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_inv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_wb_range = (void *)cpufunc_nullop,
+ .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
/* Other functions */
-
- armv7_drain_writebuf, /* drain_writebuf */
-
- (void *)cpufunc_nullop, /* sleep */
+ .cf_drain_writebuf = armv7_drain_writebuf,
+ .cf_sleep = (void *)cpufunc_nullop,
/* Soft functions */
- armv7_context_switch, /* context_switch */
-
- pj4bv7_setup /* cpu setup */
+ .cf_setup = pj4bv7_setup
};
#endif /* CPU_MV_PJ4B */
@@ -444,111 +417,50 @@ struct cpu_functions fa526_cpufuncs = {
#if defined(CPU_ARM1176)
struct cpu_functions arm1176_cpufuncs = {
- /* CPU functions */
-
- cpufunc_nullop, /* cpwait */
-
/* MMU functions */
-
- cpufunc_control, /* control */
- arm11x6_setttb, /* Setttb */
-
- /* TLB functions */
-
- arm11_tlb_flushID, /* tlb_flushID */
- arm11_tlb_flushID_SE, /* tlb_flushID_SE */
- arm11_tlb_flushD, /* tlb_flushD */
- arm11_tlb_flushD_SE, /* tlb_flushD_SE */
+ .cf_control = cpufunc_control,
+ .cf_setttb = arm11x6_setttb,
/* Cache operations */
-
- arm11x6_icache_sync_range, /* icache_sync_range */
-
- arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
- armv6_dcache_wbinv_range, /* dcache_wbinv_range */
- armv6_dcache_inv_range, /* dcache_inv_range */
- armv6_dcache_wb_range, /* dcache_wb_range */
-
- armv6_idcache_inv_all, /* idcache_inv_all */
- arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */
- arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */
-
- (void *)cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
- (void *)cpufunc_nullop, /* l2cache_drain_writebuf */
+ .cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
+ .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_inv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_wb_range = (void *)cpufunc_nullop,
+ .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
/* Other functions */
-
- arm11_drain_writebuf, /* drain_writebuf */
-
- arm11x6_sleep, /* sleep */
+ .cf_drain_writebuf = arm11_drain_writebuf,
+ .cf_sleep = arm11x6_sleep,
/* Soft functions */
-
- arm11_context_switch, /* context_switch */
-
- arm11x6_setup /* cpu setup */
+ .cf_setup = arm11x6_setup
};
#endif /*CPU_ARM1176 */
#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
struct cpu_functions cortexa_cpufuncs = {
- /* CPU functions */
-
- cpufunc_nullop, /* cpwait */
-
/* MMU functions */
-
- cpufunc_control, /* control */
- armv7_setttb, /* Setttb */
-
- /*
- * TLB functions. ARMv7 does all TLB ops based on a unified TLB model
- * whether the hardware implements separate I+D or not, so we use the
- * same 'ID' functions for all 3 variations.
- */
-
- armv7_tlb_flushID, /* tlb_flushID */
- armv7_tlb_flushID_SE, /* tlb_flushID_SE */
- armv7_tlb_flushID, /* tlb_flushD */
- armv7_tlb_flushID_SE, /* tlb_flushD_SE */
+ .cf_control = cpufunc_control,
+ .cf_setttb = armv7_setttb,
/* Cache operations */
- armv7_icache_sync_range, /* icache_sync_range */
-
- armv7_dcache_wbinv_all, /* dcache_wbinv_all */
- armv7_dcache_wbinv_range, /* dcache_wbinv_range */
- armv7_dcache_inv_range, /* dcache_inv_range */
- armv7_dcache_wb_range, /* dcache_wb_range */
-
- armv7_idcache_inv_all, /* idcache_inv_all */
- armv7_idcache_wbinv_all, /* idcache_wbinv_all */
- armv7_idcache_wbinv_range, /* idcache_wbinv_range */
-
/*
* Note: For CPUs using the PL310 the L2 ops are filled in when the
* L2 cache controller is actually enabled.
*/
- cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
- (void *)cpufunc_nullop, /* l2cache_drain_writebuf */
+ .cf_l2cache_wbinv_all = cpufunc_nullop,
+ .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_inv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_wb_range = (void *)cpufunc_nullop,
+ .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
/* Other functions */
-
- armv7_drain_writebuf, /* drain_writebuf */
-
- armv7_cpu_sleep, /* sleep */
+ .cf_drain_writebuf = armv7_drain_writebuf,
+ .cf_sleep = armv7_cpu_sleep,
/* Soft functions */
-
- armv7_context_switch, /* context_switch */
-
- cortexa_setup /* cpu setup */
+ .cf_setup = cortexa_setup
};
#endif /* CPU_CORTEXA */
@@ -767,6 +679,9 @@ set_cpufuncs(void)
case CPU_ID_CORTEXA9:
case CPU_ID_CORTEXA12:
case CPU_ID_CORTEXA15:
+ case CPU_ID_CORTEXA53:
+ case CPU_ID_CORTEXA57:
+ case CPU_ID_CORTEXA72:
case CPU_ID_KRAIT300:
cpufuncs = cortexa_cpufuncs;
get_cachetype_cp15();
Modified: stable/11/sys/arm/arm/genassym.c
==============================================================================
--- stable/11/sys/arm/arm/genassym.c Sun Apr 16 06:00:14 2017
(r317001)
+++ stable/11/sys/arm/arm/genassym.c Sun Apr 16 06:35:09 2017
(r317002)
@@ -92,11 +92,13 @@ ASSYM(M_DATA, offsetof(struct mbuf, m_da
ASSYM(M_NEXT, offsetof(struct mbuf, m_next));
ASSYM(IP_SRC, offsetof(struct ip, ip_src));
ASSYM(IP_DST, offsetof(struct ip, ip_dst));
+#if __ARM_ARCH < 6
ASSYM(CF_CONTEXT_SWITCH, offsetof(struct cpu_functions, cf_context_switch));
ASSYM(CF_DCACHE_WB_RANGE, offsetof(struct cpu_functions, cf_dcache_wb_range));
ASSYM(CF_IDCACHE_WBINV_ALL, offsetof(struct cpu_functions,
cf_idcache_wbinv_all));
ASSYM(CF_L2CACHE_WBINV_ALL, offsetof(struct cpu_functions,
cf_l2cache_wbinv_all));
ASSYM(CF_TLB_FLUSHID_SE, offsetof(struct cpu_functions, cf_tlb_flushID_SE));
+#endif
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
Modified: stable/11/sys/arm/include/armreg.h
==============================================================================
--- stable/11/sys/arm/include/armreg.h Sun Apr 16 06:00:14 2017
(r317001)
+++ stable/11/sys/arm/include/armreg.h Sun Apr 16 06:35:09 2017
(r317002)
@@ -152,6 +152,9 @@
#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 <<
CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 <<
CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 <<
CPU_ID_VARIANT_SHIFT))
+#define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME |
0xd030)
+#define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME |
0xd070)
+#define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME |
0xd080)
#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME |
0x06f0)
/* Snapdragon S4 Pro/APQ8064 */
Modified: stable/11/sys/arm/include/cpufunc.h
==============================================================================
--- stable/11/sys/arm/include/cpufunc.h Sun Apr 16 06:00:14 2017
(r317001)
+++ stable/11/sys/arm/include/cpufunc.h Sun Apr 16 06:35:09 2017
(r317002)
@@ -58,14 +58,16 @@ breakpoint(void)
struct cpu_functions {
/* CPU functions */
-
+#if __ARM_ARCH < 6
void (*cf_cpwait) (void);
+#endif
/* MMU functions */
u_int (*cf_control) (u_int bic, u_int eor);
void (*cf_setttb) (u_int ttb);
+#if __ARM_ARCH < 6
/* TLB functions */
void (*cf_tlb_flushID) (void);
@@ -138,6 +140,7 @@ struct cpu_functions {
void (*cf_idcache_inv_all) (void);
void (*cf_idcache_wbinv_all) (void);
void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
+#endif
void (*cf_l2cache_wbinv_all) (void);
void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
@@ -150,9 +153,11 @@ struct cpu_functions {
void (*cf_sleep) (int mode);
+#if __ARM_ARCH < 6
/* Soft functions */
void (*cf_context_switch) (void);
+#endif
void (*cf_setup) (void);
};
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