Author: jhibbits
Date: Wed Feb 1 03:29:13 2017
New Revision: 313036
URL: https://svnweb.freebsd.org/changeset/base/313036
Log:
Add Book-E Enhanced Debug (E.D) profile debug support
Freescale added the E.D profile to e500mc and derivative cores. From
Freescale's EREF reference manual this is enabled by a bit in HID0 and should
otherwise default to traditional debug. However, none of the Freescale cores
support that bit, and instead always use E.D. This results in kernel panics
using the standard debug on e500mc+ cores.
Enhanced debug allows debugging of interrupts, including critical interrupts,
as it uses a different save/restore registers (srr*). At this time we don't
use
this ability, so instead share the core of the debug handler code between both
handlers.
MFC after: 3 weeks
Modified:
head/sys/powerpc/booke/booke_machdep.c
head/sys/powerpc/booke/trap_subr.S
head/sys/powerpc/include/spr.h
Modified: head/sys/powerpc/booke/booke_machdep.c
==============================================================================
--- head/sys/powerpc/booke/booke_machdep.c Wed Feb 1 02:42:45 2017
(r313035)
+++ head/sys/powerpc/booke/booke_machdep.c Wed Feb 1 03:29:13 2017
(r313036)
@@ -187,6 +187,7 @@ extern void *int_watchdog;
extern void *int_data_tlb_error;
extern void *int_inst_tlb_error;
extern void *int_debug;
+extern void *int_debug_ed;
extern void *int_vec;
extern void *int_vecast;
#ifdef HWPMC_HOOKS
@@ -242,6 +243,7 @@ ivor_setup(void)
case FSL_E500mc:
case FSL_E5500:
SET_TRAP(SPR_IVOR7, int_fpu);
+ SET_TRAP(SPR_IVOR15, int_debug_ed);
break;
case FSL_E500v1:
case FSL_E500v2:
Modified: head/sys/powerpc/booke/trap_subr.S
==============================================================================
--- head/sys/powerpc/booke/trap_subr.S Wed Feb 1 02:42:45 2017
(r313035)
+++ head/sys/powerpc/booke/trap_subr.S Wed Feb 1 03:29:13 2017
(r313036)
@@ -794,6 +794,22 @@ interrupt_vector_top:
INTERRUPT(int_debug)
STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG)
+ bl int_debug_int
+ FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1)
+ rfci
+
+INTERRUPT(int_debug_ed)
+ STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_DSRR0, SPR_DSRR1)
+ FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG)
+ bl int_debug_int
+ FRAME_LEAVE(SPR_DSRR0, SPR_DSRR1)
+ rfdi
+ /* .long 0x4c00004e */
+
+/* Internal helper for debug interrupt handling. */
+/* Common code between e500v1/v2 and e500mc-based cores. */
+int_debug_int:
+ mflr %r14
GET_CPUINFO(%r3)
lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r3)
bl 0f
@@ -819,7 +835,8 @@ INTERRUPT(int_debug)
mtspr SPR_SRR0, %r3
lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r4);
mtspr SPR_SRR1, %r4
- b 9f
+ mtlr %r14
+ blr
1:
addi %r3, %r1, 8
bl CNAME(trap)
@@ -828,10 +845,6 @@ INTERRUPT(int_debug)
* We actually need to return to the process with an rfi.
*/
b trapexit
-9:
- FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1)
- rfci
-
/*****************************************************************************
* Common trap code
Modified: head/sys/powerpc/include/spr.h
==============================================================================
--- head/sys/powerpc/include/spr.h Wed Feb 1 02:42:45 2017
(r313035)
+++ head/sys/powerpc/include/spr.h Wed Feb 1 03:29:13 2017
(r313036)
@@ -671,6 +671,8 @@
#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
+#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */
+#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */
#define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */
#define MMUCR_SWOA (0x80000000 >> 7)
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