Author: jhb
Date: Tue Nov 15 17:01:48 2016
New Revision: 308690
URL: https://svnweb.freebsd.org/changeset/base/308690
Log:
Sync instruction cache's after writing user breakpoints on MIPS.
Add an implementation for pmaps_sync_icache() on MIPS that sync's the
instruction cache on all CPUs via smp_rendezvous() after a debugger
inserts a breakpoint via ptrace(PT_IO).
Tested by: kan (on Creator CI20 running Ingenic JZ4780 SOC)
MFC after: 2 weeks
Sponsored by: DARPA / AFRL
Modified:
head/sys/mips/mips/pmap.c
Modified: head/sys/mips/mips/pmap.c
==============================================================================
--- head/sys/mips/mips/pmap.c Tue Nov 15 09:43:26 2016 (r308689)
+++ head/sys/mips/mips/pmap.c Tue Nov 15 17:01:48 2016 (r308690)
@@ -74,11 +74,7 @@ __FBSDID("$FreeBSD$");
#include <sys/proc.h>
#include <sys/rwlock.h>
#include <sys/sched.h>
-#ifdef SMP
#include <sys/smp.h>
-#else
-#include <sys/cpuset.h>
-#endif
#include <sys/sysctl.h>
#include <sys/vmmeter.h>
@@ -3266,9 +3262,19 @@ pmap_activate(struct thread *td)
critical_exit();
}
+static void
+pmap_sync_icache_one(void *arg __unused)
+{
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+}
+
void
pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
{
+
+ smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
}
/*
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