On Tue, 30 Jun 2009 17:10:08 +0000 (UTC)Tue Jun 30 17:10:08 2009, Andriy Gapon wrote: > Author: avg > Date: Tue Jun 30 17:10:08 2009 > New Revision: 195197 > URL: http://svn.freebsd.org/changeset/base/195197 > > Log: > MFC 185295, 185341, 185343: cpu identification improvements > > Goal of this MFC is to minimize unnecessary code differences between > head and the branch, and to improve/fix invariant TSC detection for > a wide range of CPUs. > > 185295 by takawata: Honor AMDPM_TSC_INVARIANT for Intel CPUs (i386 only) > 185341 by jkim: Introduce cpu_vendor_id... > 185343 by jkim: Use newly introduced cpu_vendor_id... > > These revision are bundled together because all intermediate revisions > have one or more of the following deficiencies: > o AMDPM_TSC_INVARIANT bit (CPUID.0x80000007.EDX[8]) is not honored for > Intel CPUs; > o AMD-specific CPU model/revision checks are performed on Intel CPUs. > > Nod from: jkim > > Modified: > stable/7/sys/ (props changed) > stable/7/sys/amd64/amd64/amd64_mem.c > stable/7/sys/amd64/amd64/identcpu.c > stable/7/sys/amd64/amd64/initcpu.c > stable/7/sys/amd64/amd64/local_apic.c > stable/7/sys/amd64/amd64/mp_machdep.c > stable/7/sys/amd64/amd64/msi.c > stable/7/sys/amd64/include/cputypes.h > stable/7/sys/amd64/include/md_var.h > stable/7/sys/amd64/include/specialreg.h > stable/7/sys/contrib/pf/ (props changed) > stable/7/sys/dev/coretemp/coretemp.c > stable/7/sys/dev/hwpmc/hwpmc_intel.c > stable/7/sys/dev/hwpmc/hwpmc_piv.c > stable/7/sys/dev/hwpmc/hwpmc_ppro.c > stable/7/sys/dev/hwpmc/hwpmc_x86.c > stable/7/sys/i386/cpufreq/est.c > stable/7/sys/i386/i386/i686_mem.c > stable/7/sys/i386/i386/identcpu.c > stable/7/sys/i386/i386/initcpu.c > stable/7/sys/i386/i386/k6_mem.c > stable/7/sys/i386/i386/local_apic.c > stable/7/sys/i386/i386/longrun.c > stable/7/sys/i386/i386/mp_machdep.c > stable/7/sys/i386/i386/msi.c > stable/7/sys/i386/include/cputypes.h > stable/7/sys/i386/include/md_var.h > stable/7/sys/i386/include/specialreg.h > > Modified: stable/7/sys/amd64/amd64/amd64_mem.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/amd64_mem.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/amd64/amd64_mem.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/smp.h> > #include <sys/sysctl.h> > > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -677,8 +678,8 @@ amd64_mem_drvinit(void *unused) > return; > if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00) > return; > - if ((strcmp(cpu_vendor, "GenuineIntel") != 0) && > - (strcmp(cpu_vendor, "AuthenticAMD") != 0)) > + if (cpu_vendor_id != CPU_VENDOR_INTEL && > + cpu_vendor_id != CPU_VENDOR_AMD) > return; > mem_range_softc.mr_op = &amd64_mrops; > } > > Modified: stable/7/sys/amd64/amd64/identcpu.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/identcpu.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/amd64/identcpu.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -69,6 +69,7 @@ void identify_cpu(void); > void earlysetcpuclass(void); > void panicifcpuunsupported(void); > > +static u_int find_cpu_vendor_id(void); > static void print_AMD_info(void); > static void print_AMD_assoc(int i); > > @@ -95,6 +96,14 @@ static struct { > { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ > }; > > +static struct { > + char *vendor; > + u_int vendor_id; > +} cpu_vendors[] = { > + { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ > + { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ > +}; > + > void > printcpuinfo(void) > { > @@ -115,10 +124,10 @@ printcpuinfo(void) > } > } > > - if (strcmp(cpu_vendor, "GenuineIntel") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_INTEL) { > /* Please make up your mind folks! */ > strcat(cpu_model, "EM64T"); > - } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_AMD) { > /* > * Values taken from AMD Processor Recognition > * http://www.amd.com/K6/k6docs/pdf/20734g.pdf > @@ -158,13 +167,13 @@ printcpuinfo(void) > printf("Unknown"); /* will panic below... */ > } > printf("-class CPU)\n"); > - if(*cpu_vendor) > - printf(" Origin = \"%s\"",cpu_vendor); > - if(cpu_id) > + if (*cpu_vendor) > + printf(" Origin = \"%s\"", cpu_vendor); > + if (cpu_id) > printf(" Id = 0x%x", cpu_id); > > - if (strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD) { > printf(" Stepping = %u", cpu_id & 0xf); > if (cpu_high > 0) { > u_int cmp = 1, htt = 1; > @@ -336,22 +345,28 @@ printcpuinfo(void) > ); > } > > - if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, > - "AuthenticAMD") == 0) > + if ((cpu_feature & CPUID_HTT) && > + cpu_vendor_id == CPU_VENDOR_AMD) > cpu_feature &= ~CPUID_HTT; > > /* > * If this CPU supports P-state invariant TSC then > * mention the capability. > */ > - if (!tsc_is_invariant && > - (strcmp(cpu_vendor, "AuthenticAMD") == 0 && > - ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || > - AMD64_CPU_FAMILY(cpu_id) >= 0x10 || > - cpu_id == 0x60fb2))) { > - tsc_is_invariant = 1; > - printf("\n TSC: P-state invariant"); > + switch (cpu_vendor_id) { > + case CPU_VENDOR_AMD: > + if ((amd_pminfo & AMDPM_TSC_INVARIANT) || > + AMD64_CPU_FAMILY(cpu_id) >= 0x10 || > + cpu_id == 0x60fb2) > + tsc_is_invariant = 1; > + break; > + case CPU_VENDOR_INTEL: > + if (amd_pminfo & AMDPM_TSC_INVARIANT) > + tsc_is_invariant = 1; > + break; > } > + if (tsc_is_invariant) > + printf("\n TSC: P-state invariant"); > > /* > * If this CPU supports HTT or CMP then mention the > @@ -359,10 +374,10 @@ printcpuinfo(void) > */ > if (cpu_feature & CPUID_HTT) > htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && > + if (cpu_vendor_id == CPU_VENDOR_AMD && > (amd_feature2 & AMDID2_CMP)) > cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; > - else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && > + else if (cpu_vendor_id == CPU_VENDOR_INTEL && > (cpu_high >= 4)) { > cpuid_count(4, 0, regs); > if ((regs[0] & 0x1f) != 0) > @@ -382,7 +397,7 @@ printcpuinfo(void) > if (!bootverbose) > return; > > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) > + if (cpu_vendor_id == CPU_VENDOR_AMD) > print_AMD_info(); > } > > @@ -441,6 +456,7 @@ identify_cpu(void) > ((u_int *)&cpu_vendor)[1] = regs[3]; > ((u_int *)&cpu_vendor)[2] = regs[2]; > cpu_vendor[12] = '\0'; > + cpu_vendor_id = find_cpu_vendor_id(); > > do_cpuid(1, regs); > cpu_id = regs[0]; > @@ -448,8 +464,8 @@ identify_cpu(void) > cpu_feature = regs[3]; > cpu_feature2 = regs[2]; > > - if (strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD) { > do_cpuid(0x80000000, regs); > cpu_exthigh = regs[0]; > } > @@ -471,6 +487,17 @@ identify_cpu(void) > cpu = CPU_CLAWHAMMER; > } > > +static u_int > +find_cpu_vendor_id(void) > +{ > + int i; > + > + for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) > + if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) > + return (cpu_vendors[i].vendor_id); > + return (0); > +} > + > static void > print_AMD_assoc(int i) > { > > Modified: stable/7/sys/amd64/amd64/initcpu.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/initcpu.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/amd64/initcpu.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -60,6 +60,7 @@ u_int cpu_id; /* > Stepping ID */ > u_int cpu_procinfo; /* HyperThreading Info / Brand Index / > CLFUSH */ > u_int cpu_procinfo2; /* Multicore info */ > char cpu_vendor[20]; /* CPU Origin code */ > +u_int cpu_vendor_id; /* CPU vendor ID */ > u_int cpu_fxsr; /* SSE enabled */ > u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ > > > Modified: stable/7/sys/amd64/amd64/local_apic.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/local_apic.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/amd64/local_apic.c Tue Jun 30 > 17:10:08 2009 (r195197) @@ -323,7 +323,7 @@ lapic_setup(int boot) > > /* XXX: Error and thermal LVTs */ > > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_AMD) { > /* > * Detect the presence of C1E capability mostly on latest > * dual-cores (or future) k8 family. This feature renders > > Modified: stable/7/sys/amd64/amd64/mp_machdep.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/mp_machdep.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/amd64/mp_machdep.c Tue Jun 30 > 17:10:08 2009 (r195197) @@ -57,6 +57,7 @@ __FBSDID("$FreeBSD$"); > #include <vm/vm_extern.h> > > #include <machine/apicreg.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/mp_watchdog.h> > #include <machine/pcb.h> > @@ -376,8 +377,7 @@ cpu_mp_start(void) > * First determine if this is an Intel processor which claims > * to have hyperthreading support. > */ > - if ((cpu_feature & CPUID_HTT) && > - (strcmp(cpu_vendor, "GenuineIntel") == 0)) { > + if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { > /* > * If the "deterministic cache parameters" cpuid calls > * are available, use them. > > Modified: stable/7/sys/amd64/amd64/msi.c > =========================================================================== >=== --- stable/7/sys/amd64/amd64/msi.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/amd64/amd64/msi.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/sx.h> > #include <sys/systm.h> > #include <machine/apicreg.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/frame.h> > #include <machine/intr_machdep.h> > @@ -211,8 +212,8 @@ msi_init(void) > { > > /* Check if we have a supported CPU. */ > - if (!(strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0)) > + if (!(cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD)) > return; > > msi_enabled = 1; > > Modified: stable/7/sys/amd64/include/cputypes.h > =========================================================================== >=== --- stable/7/sys/amd64/include/cputypes.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/include/cputypes.h Tue Jun 30 > 17:10:08 2009 (r195197) @@ -33,15 +33,21 @@ > /* > * Classes of processor. > */ > -#define CPUCLASS_X86 0 /* X86 */ > -#define CPUCLASS_K8 1 /* K8 AMD64 class */ > +#define CPUCLASS_X86 0 /* X86 */ > +#define CPUCLASS_K8 1 /* K8 AMD64 class */ > > /* > * Kinds of processor. > */ > -#define CPU_X86 0 /* Intel */ > -#define CPU_CLAWHAMMER 1 /* AMD Clawhammer */ > -#define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */ > +#define CPU_X86 0 /* Intel */ > +#define CPU_CLAWHAMMER 1 /* AMD Clawhammer */ > +#define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */ > + > +/* > + * Vendors of processor. > + */ > +#define CPU_VENDOR_AMD 0x1022 /* AMD */ > +#define CPU_VENDOR_INTEL 0x8086 /* Intel */ > > #ifndef LOCORE > extern int cpu; > > Modified: stable/7/sys/amd64/include/md_var.h > =========================================================================== >=== --- stable/7/sys/amd64/include/md_var.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/include/md_var.h Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -52,6 +52,7 @@ extern u_int cpu_mxcsr_mask; > extern u_int cpu_procinfo; > extern u_int cpu_procinfo2; > extern char cpu_vendor[]; > +extern u_int cpu_vendor_id; > extern char kstack[]; > extern char sigcode[]; > extern int szsigcode; > > Modified: stable/7/sys/amd64/include/specialreg.h > =========================================================================== >=== --- stable/7/sys/amd64/include/specialreg.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/amd64/include/specialreg.h Tue Jun 30 > 17:10:08 2009 (r195197) @@ -204,8 +204,8 @@ > /* > * CPUID manufacturers identifiers > */ > -#define INTEL_VENDOR_ID "GenuineIntel" > -#define AMD_VENDOR_ID "AuthenticAMD" > +#define AMD_VENDOR_ID "AuthenticAMD" > +#define INTEL_VENDOR_ID "GenuineIntel" > > /* > * Model-specific registers for the i386 family > > Modified: stable/7/sys/dev/coretemp/coretemp.c > =========================================================================== >=== --- stable/7/sys/dev/coretemp/coretemp.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/dev/coretemp/coretemp.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$"); > > #include <machine/specialreg.h> > #include <machine/cpufunc.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > > struct coretemp_softc { > @@ -94,7 +95,7 @@ coretemp_identify(driver_t *driver, devi > return; > > /* Check that CPUID 0x06 is supported and the vendor is Intel.*/ > - if (cpu_high < 6 || strcmp(cpu_vendor, "GenuineIntel")) > + if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL) > return; > /* > * CPUID 0x06 returns 1 if the processor has on-die thermal > > Modified: stable/7/sys/dev/hwpmc/hwpmc_intel.c > =========================================================================== >=== --- stable/7/sys/dev/hwpmc/hwpmc_intel.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/dev/hwpmc/hwpmc_intel.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/systm.h> > > #include <machine/cpu.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -79,7 +80,7 @@ pmc_intel_initialize(void) > enum pmc_cputype cputype; > int error, model, nclasses, ncpus; > > - KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0, > + KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, > ("[intel,%d] Initializing non-intel processor", __LINE__)); > > PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); > > Modified: stable/7/sys/dev/hwpmc/hwpmc_piv.c > =========================================================================== >=== --- stable/7/sys/dev/hwpmc/hwpmc_piv.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/dev/hwpmc/hwpmc_piv.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$"); > > #include <machine/cpu.h> > #include <machine/cpufunc.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -1610,7 +1611,7 @@ pmc_p4_initialize(struct pmc_mdep *md, i > struct p4_event_descr *pe; > > KASSERT(md != NULL, ("[p4,%d] md is NULL", __LINE__)); > - KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0, > + KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, > ("[p4,%d] Initializing non-intel processor", __LINE__)); > > PMCDBG(MDP,INI,1, "%s", "p4-initialize"); > > Modified: stable/7/sys/dev/hwpmc/hwpmc_ppro.c > =========================================================================== >=== --- stable/7/sys/dev/hwpmc/hwpmc_ppro.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/dev/hwpmc/hwpmc_ppro.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$"); > > #include <machine/cpu.h> > #include <machine/cpufunc.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/pmc_mdep.h> > #include <machine/specialreg.h> > @@ -781,7 +782,7 @@ pmc_p6_initialize(struct pmc_mdep *md, i > { > struct pmc_classdep *pcd; > > - KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0, > + KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, > ("[p6,%d] Initializing non-intel processor", __LINE__)); > > PMCDBG(MDP,INI,1, "%s", "p6-initialize"); > > Modified: stable/7/sys/dev/hwpmc/hwpmc_x86.c > =========================================================================== >=== --- stable/7/sys/dev/hwpmc/hwpmc_x86.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/dev/hwpmc/hwpmc_x86.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/systm.h> > > #include <machine/cpu.h> > +#include <machine/cputypes.h> > #include <machine/apicreg.h> > #include <machine/pmc_mdep.h> > #include <machine/md_var.h> > @@ -252,9 +253,9 @@ pmc_md_initialize() > > /* determine the CPU kind */ > md = NULL; > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) > + if (cpu_vendor_id == CPU_VENDOR_AMD) > md = pmc_amd_initialize(); > - else if (strcmp(cpu_vendor, "GenuineIntel") == 0) > + else if (cpu_vendor_id == CPU_VENDOR_INTEL) > md = pmc_intel_initialize(); > else > KASSERT(0, ("[x86,%d] Unknown vendor", __LINE__)); > @@ -270,9 +271,9 @@ pmc_md_initialize() > void > pmc_md_finalize(struct pmc_mdep *md) > { > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) > + if (cpu_vendor_id == CPU_VENDOR_AMD) > pmc_amd_finalize(md); > - else if (strcmp(cpu_vendor, "GenuineIntel") == 0) > + else if (cpu_vendor_id == CPU_VENDOR_INTEL) > pmc_intel_finalize(md); > else > KASSERT(0, ("[x86,%d] Unknown vendor", __LINE__)); > > Modified: stable/7/sys/i386/cpufreq/est.c > =========================================================================== >=== --- stable/7/sys/i386/cpufreq/est.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/cpufreq/est.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -39,6 +39,7 @@ __FBSDID("$FreeBSD$"); > > #include "cpufreq_if.h" > #include <machine/clock.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -54,6 +55,10 @@ __FBSDID("$FreeBSD$"); > #define MSR_MISC_ENABLE 0x1a0 > #define MSR_SS_ENABLE (1<<16) > > +#ifndef CPU_VENDOR_CENTAUR > +#define CPU_VENDOR_CENTAUR 0x111d > +#endif > + > /* Frequency and MSR control values. */ > typedef struct { > uint16_t freq; > @@ -64,7 +69,7 @@ typedef struct { > > /* Identifying characteristics of a processor and supported frequencies. > */ typedef struct { > - const char *vendor; > + const u_int vendor_id; > uint32_t id32; > freq_info *freqtab; > } cpu_info; > @@ -88,12 +93,10 @@ struct est_softc { > #define FREQ_INFO(MHz, mV, bus_clk) \ > FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) > #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ > - { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } > + { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } > #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ > - { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } > + { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } > > -const char intel_id[] = "GenuineIntel"; > -const char centaur_id[] = "CentaurHauls"; > static int msr_info_enabled = 0; > TUNABLE_INT("hw.est.msr_info", &msr_info_enabled); > > @@ -891,7 +894,7 @@ static cpu_info ESTprocs[] = { > CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), > CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), > CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), > - { NULL, 0, NULL }, > + { 0, 0, NULL }, > }; > > static void est_identify(driver_t *driver, device_t parent); > @@ -958,8 +961,8 @@ est_identify(driver_t *driver, device_t > return; > > /* Check that CPUID is supported and the vendor is Intel.*/ > - if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 && > - strcmp(cpu_vendor, centaur_id) != 0)) > + if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && > + cpu_vendor_id != CPU_VENDOR_CENTAUR)) > return; > > /* > @@ -1159,7 +1162,7 @@ est_table_info(device_t dev, uint64_t ms > /* Find a table which matches (vendor, id32). */ > id = msr >> 32; > for (p = ESTprocs; p->id32 != 0; p++) { > - if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id) > + if (p->vendor_id == cpu_vendor_id && p->id32 == id) > break; > } > if (p->id32 == 0) > > Modified: stable/7/sys/i386/i386/i686_mem.c > =========================================================================== >=== --- stable/7/sys/i386/i386/i686_mem.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/i386/i686_mem.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -35,6 +35,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/smp.h> > #include <sys/sysctl.h> > > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -677,8 +678,8 @@ i686_mem_drvinit(void *unused) > return; > if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00) > return; > - if ((strcmp(cpu_vendor, "GenuineIntel") != 0) && > - (strcmp(cpu_vendor, "AuthenticAMD") != 0)) > + if (cpu_vendor_id != CPU_VENDOR_INTEL && > + cpu_vendor_id != CPU_VENDOR_AMD) > return; > mem_range_softc.mr_op = &i686_mrops; > } > > Modified: stable/7/sys/i386/i386/identcpu.c > =========================================================================== >=== --- stable/7/sys/i386/i386/identcpu.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/i386/identcpu.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -77,6 +77,7 @@ void panicifcpuunsupported(void); > > static void identifycyrix(void); > static void init_exthigh(void); > +static u_int find_cpu_vendor_id(void); > static void print_AMD_info(void); > static void print_INTEL_info(void); > static void print_INTEL_TLB(u_int data); > @@ -138,6 +139,26 @@ static struct { > { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ > }; > > +static struct { > + char *vendor; > + u_int vendor_id; > +} cpu_vendors[] = { > + { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ > + { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ > + { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ > + { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ > + { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ > + { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ > + { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ > + { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ > + { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ > + { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ > +#if 0 > + /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ > + { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, > +#endif > +}; > + > #if defined(I586_CPU) && !defined(NO_F00F_HACK) > int has_f00f_bug = 0; /* Initialized so that it can be > patched. */ > #endif > @@ -150,12 +171,11 @@ init_exthigh(void) > > if (done == 0) { > if (cpu_high > 0 && > - (strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0 || > - strcmp(cpu_vendor, "GenuineTMx86") == 0 || > - strcmp(cpu_vendor, "TransmetaCPU") == 0 || > - strcmp(cpu_vendor, "CentaurHauls") == 0 || > - strcmp(cpu_vendor, "Geode by NSC") == 0)) { > + (cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD || > + cpu_vendor_id == CPU_VENDOR_TRANSMETA || > + cpu_vendor_id == CPU_VENDOR_CENTAUR || > + cpu_vendor_id == CPU_VENDOR_NSC)) { > do_cpuid(0x80000000, regs); > if (regs[0] >= 0x80000000) > cpu_exthigh = regs[0]; > @@ -186,7 +206,7 @@ printcpuinfo(void) > } > } > > - if (strcmp(cpu_vendor, "GenuineIntel") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_INTEL) { > if ((cpu_id & 0xf00) > 0x300) { > u_int brand_index; > u_int model; > @@ -330,7 +350,7 @@ printcpuinfo(void) > cpu_brandtable[brand_index]); > } > } > - } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_AMD) { > /* > * Values taken from AMD Processor Recognition > * http://www.amd.com/K6/k6docs/pdf/20734g.pdf > @@ -410,7 +430,7 @@ printcpuinfo(void) > enable_K6_wt_alloc(); > } > #endif > - } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { > strcpy(cpu_model, "Cyrix "); > switch (cpu_id & 0xff0) { > case 0x440: > @@ -546,7 +566,7 @@ printcpuinfo(void) > } > break; > } > - } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_RISE) { > strcpy(cpu_model, "Rise "); > switch (cpu_id & 0xff0) { > case 0x500: > @@ -555,7 +575,7 @@ printcpuinfo(void) > default: > strcat(cpu_model, "Unknown"); > } > - } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { > switch (cpu_id & 0xff0) { > case 0x540: > strcpy(cpu_model, "IDT WinChip C6"); > @@ -586,9 +606,9 @@ printcpuinfo(void) > default: > strcpy(cpu_model, "VIA/IDT Unknown"); > } > - } else if (strcmp(cpu_vendor, "IBM") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_IBM) { > strcpy(cpu_model, "Blue Lightning CPU"); > - } else if (strcmp(cpu_vendor, "Geode by NSC") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_NSC) { > switch (cpu_id & 0xfff) { > case 0x540: > strcpy(cpu_model, "Geode SC1100"); > @@ -652,17 +672,16 @@ printcpuinfo(void) > if(cpu_id) > printf(" Id = 0x%x", cpu_id); > > - if (strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0 || > - strcmp(cpu_vendor, "GenuineTMx86") == 0 || > - strcmp(cpu_vendor, "TransmetaCPU") == 0 || > - strcmp(cpu_vendor, "RiseRiseRise") == 0 || > - strcmp(cpu_vendor, "CentaurHauls") == 0 || > - strcmp(cpu_vendor, "Geode by NSC") == 0 || > - ((strcmp(cpu_vendor, "CyrixInstead") == 0) && > + if (cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD || > + cpu_vendor_id == CPU_VENDOR_TRANSMETA || > + cpu_vendor_id == CPU_VENDOR_RISE || > + cpu_vendor_id == CPU_VENDOR_CENTAUR || > + cpu_vendor_id == CPU_VENDOR_NSC || > + (cpu_vendor_id == CPU_VENDOR_CYRIX && > ((cpu_id & 0xf00) > 0x500))) { > printf(" Stepping = %u", cpu_id & 0xf); > - if (strcmp(cpu_vendor, "CyrixInstead") == 0) > + if (cpu_vendor_id == CPU_VENDOR_CYRIX) > printf(" DIR=0x%04x", cyrix_did); > if (cpu_high > 0) { > u_int cmp = 1, htt = 1; > @@ -834,22 +853,28 @@ printcpuinfo(void) > ); > } > > - if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, > - "AuthenticAMD") == 0) > + if ((cpu_feature & CPUID_HTT) && > + cpu_vendor_id == CPU_VENDOR_AMD) > cpu_feature &= ~CPUID_HTT; > > /* > * If this CPU supports P-state invariant TSC then > * mention the capability. > */ > - if (!tsc_is_invariant && > - (strcmp(cpu_vendor, "AuthenticAMD") == 0 && > - ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || > - I386_CPU_FAMILY(cpu_id) >= 0x10 || > - cpu_id == 0x60fb2))) { > - tsc_is_invariant = 1; > - printf("\n TSC: P-state invariant"); > + switch (cpu_vendor_id) { > + case CPU_VENDOR_AMD: > + if ((amd_pminfo & AMDPM_TSC_INVARIANT) || > + I386_CPU_FAMILY(cpu_id) >= 0x10 || > + cpu_id == 0x60fb2) > + tsc_is_invariant = 1; > + break; > + case CPU_VENDOR_INTEL: > + if (amd_pminfo & AMDPM_TSC_INVARIANT) > + tsc_is_invariant = 1; > + break; > } > + if (tsc_is_invariant) > + printf("\n TSC: P-state invariant"); > > /* > * If this CPU supports HTT or CMP then mention the > @@ -857,10 +882,10 @@ printcpuinfo(void) > */ > if (cpu_feature & CPUID_HTT) > htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && > + if (cpu_vendor_id == CPU_VENDOR_AMD && > (amd_feature2 & AMDID2_CMP)) > cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; > - else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && > + else if (cpu_vendor_id == CPU_VENDOR_INTEL && > (cpu_high >= 4)) { > cpuid_count(4, 0, regs); > if ((regs[0] & 0x1f) != 0) > @@ -872,7 +897,7 @@ printcpuinfo(void) > printf("\n Logical CPUs per core: %d", > htt / cmp); > } > - } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { > printf(" DIR=0x%04x", cyrix_did); > printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); > printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); > @@ -881,7 +906,7 @@ printcpuinfo(void) > printf("\n CPU cache: write-through mode"); > #endif > } > - if (strcmp(cpu_vendor, "CentaurHauls") == 0) > + if (cpu_vendor_id == CPU_VENDOR_CENTAUR) > print_via_padlock_info(); > > /* Avoid ugly blank lines: only print newline when we have to. */ > @@ -891,12 +916,11 @@ printcpuinfo(void) > if (!bootverbose) > return; > > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) > + if (cpu_vendor_id == CPU_VENDOR_AMD) > print_AMD_info(); > - else if (strcmp(cpu_vendor, "GenuineIntel") == 0) > + else if (cpu_vendor_id == CPU_VENDOR_INTEL) > print_INTEL_info(); > - else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 || > - strcmp(cpu_vendor, "TransmetaCPU") == 0) > + else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) > print_transmeta_info(); > } > > @@ -1091,9 +1115,11 @@ finishidentcpu(void) > u_char ccr3; > u_int regs[4]; > > + cpu_vendor_id = find_cpu_vendor_id(); > + > /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ > - if (strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD) { > init_exthigh(); > if (cpu_exthigh >= 0x80000001) { > do_cpuid(0x80000001, regs); > @@ -1108,7 +1134,7 @@ finishidentcpu(void) > do_cpuid(0x80000008, regs); > cpu_procinfo2 = regs[2]; > } > - } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) { > + } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { > if (cpu == CPU_486) { > /* > * These conditions are equivalent to: > @@ -1118,6 +1144,7 @@ finishidentcpu(void) > isblue = identblue(); > if (isblue == IDENTBLUE_IBMCPU) { > strcpy(cpu_vendor, "IBM"); > + cpu_vendor_id = CPU_VENDOR_IBM; > cpu = CPU_BLUE; > return; > } > @@ -1191,12 +1218,24 @@ finishidentcpu(void) > isblue = identblue(); > if (isblue == IDENTBLUE_IBMCPU) { > strcpy(cpu_vendor, "IBM"); > + cpu_vendor_id = CPU_VENDOR_IBM; > cpu = CPU_BLUE; > return; > } > } > } > > +static u_int > +find_cpu_vendor_id(void) > +{ > + int i; > + > + for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) > + if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) > + return (cpu_vendors[i].vendor_id); > + return (0); > +} > + > static void > print_AMD_assoc(int i) > { > > Modified: stable/7/sys/i386/i386/initcpu.c > =========================================================================== >=== --- stable/7/sys/i386/i386/initcpu.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/i386/initcpu.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -90,6 +90,7 @@ u_int cpu_id = 0; /* Stepping ID */ > u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / > CLFUSH */ > u_int cpu_procinfo2 = 0; /* Multicore info */ > char cpu_vendor[20] = ""; /* CPU Origin code */ > +u_int cpu_vendor_id = 0; /* CPU vendor ID */ > > SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, > &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); > > Modified: stable/7/sys/i386/i386/k6_mem.c > =========================================================================== >=== --- stable/7/sys/i386/i386/k6_mem.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/i386/k6_mem.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -33,6 +33,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/malloc.h> > #include <sys/memrange.h> > > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -175,7 +176,7 @@ static void > k6_mem_drvinit(void *unused) > { > > - if (strcmp(cpu_vendor, "AuthenticAMD") != 0) > + if (cpu_vendor_id != CPU_VENDOR_AMD) > return; > if ((cpu_id & 0xf00) != 0x500) > return; > > Modified: stable/7/sys/i386/i386/local_apic.c > =========================================================================== >=== --- stable/7/sys/i386/i386/local_apic.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/i386/i386/local_apic.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -325,7 +325,7 @@ lapic_setup(int boot) > > /* XXX: Error and thermal LVTs */ > > - if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { > + if (cpu_vendor_id == CPU_VENDOR_AMD) { > /* > * Detect the presence of C1E capability mostly on latest > * dual-cores (or future) k8 family. This feature renders > @@ -1073,7 +1073,7 @@ apic_init(void *dummy __unused) > * CPUs during early startup. We need to turn the local APIC back > * on on such CPUs now. > */ > - if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && > + if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && > (cpu_id & 0xff0) == 0x610) { > apic_base = rdmsr(MSR_APICBASE); > apic_base |= APICBASE_ENABLED; > > Modified: stable/7/sys/i386/i386/longrun.c > =========================================================================== >=== --- stable/7/sys/i386/i386/longrun.c Tue Jun 30 15:23:16 2009 >(r195196) > +++ stable/7/sys/i386/i386/longrun.c Tue Jun 30 17:10:08 2009 > (r195197) @@ > -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/sysctl.h> > #include <sys/types.h> > > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/specialreg.h> > > @@ -262,8 +263,8 @@ tmx86_longrun_profile_sysctl(SYSCTL_HAND > static void > setup_tmx86_longrun(void *dummy __unused) > { > - if (strcmp(cpu_vendor, "GenuineTMx86") != 0 && > - strcmp(cpu_vendor, "TransmetaCPU") != 0) > + > + if (cpu_vendor_id != CPU_VENDOR_TRANSMETA) > return; > > crusoe_longrun = tmx86_get_longrun_mode(); > > Modified: stable/7/sys/i386/i386/mp_machdep.c > =========================================================================== >=== --- stable/7/sys/i386/i386/mp_machdep.c Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/i386/i386/mp_machdep.c Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -72,6 +72,7 @@ __FBSDID("$FreeBSD$"); > #include <vm/vm_extern.h> > > #include <machine/apicreg.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/mp_watchdog.h> > #include <machine/pcb.h> > @@ -425,8 +426,7 @@ cpu_mp_start(void) > * First determine if this is an Intel processor which claims > * to have hyperthreading support. > */ > - if ((cpu_feature & CPUID_HTT) && > - (strcmp(cpu_vendor, "GenuineIntel") == 0)) { > + if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { > /* > * If the "deterministic cache parameters" cpuid calls > * are available, use them. > > Modified: stable/7/sys/i386/i386/msi.c > =========================================================================== >=== --- stable/7/sys/i386/i386/msi.c Tue Jun 30 15:23:16 2009 >(r195196) +++ > stable/7/sys/i386/i386/msi.c Tue Jun 30 17:10:08 2009 (r195197) @@ > -46,6 > +46,7 @@ __FBSDID("$FreeBSD$"); > #include <sys/sx.h> > #include <sys/systm.h> > #include <machine/apicreg.h> > +#include <machine/cputypes.h> > #include <machine/md_var.h> > #include <machine/frame.h> > #include <machine/intr_machdep.h> > @@ -211,8 +212,8 @@ msi_init(void) > { > > /* Check if we have a supported CPU. */ > - if (!(strcmp(cpu_vendor, "GenuineIntel") == 0 || > - strcmp(cpu_vendor, "AuthenticAMD") == 0)) > + if (!(cpu_vendor_id == CPU_VENDOR_INTEL || > + cpu_vendor_id == CPU_VENDOR_AMD)) > return; > > msi_enabled = 1; > > Modified: stable/7/sys/i386/include/cputypes.h > =========================================================================== >=== --- stable/7/sys/i386/include/cputypes.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/i386/include/cputypes.h Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -33,33 +33,49 @@ > /* > * Classes of processor. > */ > -#define CPUCLASS_286 0 > -#define CPUCLASS_386 1 > -#define CPUCLASS_486 2 > -#define CPUCLASS_586 3 > -#define CPUCLASS_686 4 > +#define CPUCLASS_286 0 > +#define CPUCLASS_386 1 > +#define CPUCLASS_486 2 > +#define CPUCLASS_586 3 > +#define CPUCLASS_686 4 > > /* > * Kinds of processor. > */ > -#define CPU_286 0 /* Intel 80286 */ > -#define CPU_386SX 1 /* Intel 80386SX */ > -#define CPU_386 2 /* Intel 80386DX */ > -#define CPU_486SX 3 /* Intel 80486SX */ > -#define CPU_486 4 /* Intel 80486DX */ > -#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's > TM) */ > -#define CPU_486DLC 6 /* Cyrix 486DLC */ > -#define CPU_686 7 /* Pentium Pro */ > -#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */ > -#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */ > -#define CPU_BLUE 10 /* IBM BlueLighting CPU */ > -#define CPU_M2 11 /* Cyrix M2 (aka enhanced 6x86 with MMX > */ > -#define CPU_NX586 12 /* NexGen (now AMD) 586 */ > -#define CPU_CY486DX 13 /* Cyrix 486S/DX/DX2/DX4 */ > -#define CPU_PII 14 /* Intel Pentium II */ > -#define CPU_PIII 15 /* Intel Pentium III */ > -#define CPU_P4 16 /* Intel Pentium 4 */ > -#define CPU_GEODE1100 17 /* NS Geode SC1100 */ > +#define CPU_286 0 /* Intel 80286 */ > +#define CPU_386SX 1 /* Intel 80386SX */ > +#define CPU_386 2 /* Intel 80386DX */ > +#define CPU_486SX 3 /* Intel 80486SX */ > +#define CPU_486 4 /* Intel 80486DX */ > +#define CPU_586 5 /* Intel Pentium */ > +#define CPU_486DLC 6 /* Cyrix 486DLC */ > +#define CPU_686 7 /* Pentium Pro */ > +#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */ > +#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */ > +#define CPU_BLUE 10 /* IBM BlueLighting CPU */ > +#define CPU_M2 11 /* Cyrix M2 (enhanced 6x86 with > MMX) */ > +#define CPU_NX586 12 /* NexGen (now AMD) 586 */ > +#define CPU_CY486DX 13 /* Cyrix 486S/DX/DX2/DX4 */ > +#define CPU_PII 14 /* Intel Pentium II */ > +#define CPU_PIII 15 /* Intel Pentium III */ > +#define CPU_P4 16 /* Intel Pentium 4 */ > +#define CPU_GEODE1100 17 /* NS Geode SC1100 */ > + > +/* > + * Vendors of processor. > + */ > +#define CPU_VENDOR_NSC 0x100b /* NSC */ > +#define CPU_VENDOR_IBM 0x1014 /* IBM */ > +#define CPU_VENDOR_AMD 0x1022 /* AMD */ > +#define CPU_VENDOR_SIS 0x1039 /* SiS */ > +#define CPU_VENDOR_UMC 0x1060 /* UMC */ > +#define CPU_VENDOR_NEXGEN 0x1074 /* Nexgen */ > +#define CPU_VENDOR_CYRIX 0x1078 /* Cyrix */ > +#define CPU_VENDOR_IDT 0x111d /* Centaur/IDT/VIA */ > +#define CPU_VENDOR_TRANSMETA 0x1279 /* Transmeta */ > +#define CPU_VENDOR_INTEL 0x8086 /* Intel */ > +#define CPU_VENDOR_RISE 0xdead2bad /* Rise */ > +#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT > > #ifndef LOCORE > extern int cpu; > > Modified: stable/7/sys/i386/include/md_var.h > =========================================================================== >=== --- stable/7/sys/i386/include/md_var.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/i386/include/md_var.h Tue Jun 30 > 17:10:08 > 2009 (r195197) @@ -59,6 +59,7 @@ extern u_int cpu_mxcsr_mask; > extern u_int cpu_procinfo; > extern u_int cpu_procinfo2; > extern char cpu_vendor[]; > +extern u_int cpu_vendor_id; > extern u_int cyrix_did; > extern char kstack[]; > extern char sigcode[]; > > Modified: stable/7/sys/i386/include/specialreg.h > =========================================================================== >=== --- stable/7/sys/i386/include/specialreg.h Tue Jun 30 15:23:16 > 2009 (r195196) +++ stable/7/sys/i386/include/specialreg.h Tue Jun 30 > 17:10:08 2009 (r195197) @@ -203,8 +203,16 @@ > /* > * CPUID manufacturers identifiers > */ > -#define INTEL_VENDOR_ID "GenuineIntel" > -#define AMD_VENDOR_ID "AuthenticAMD" > +#define AMD_VENDOR_ID "AuthenticAMD" > +#define CENTAUR_VENDOR_ID "CentaurHauls" > +#define CYRIX_VENDOR_ID "CyrixInstead" > +#define INTEL_VENDOR_ID "GenuineIntel" > +#define NEXGEN_VENDOR_ID "NexGenDriven" > +#define NSC_VENDOR_ID "Geode by NSC" > +#define RISE_VENDOR_ID "RiseRiseRise" > +#define SIS_VENDOR_ID "SiS SiS SiS " > +#define TRANSMETA_VENDOR_ID "GenuineTMx86" > +#define UMC_VENDOR_ID "UMC UMC UMC " > > /* > * Model-specific registers for the i386 family
buildkernel fails for me with latest stable: ===> coretemp (all) cc -O2 -fno-strict-aliasing -pipe -march=prescott -D_KERNEL -DKLD_MODULE - std=c99 -nostdinc -DHAVE_KERNEL_OPTION_HEADERS -include /usr/obj/usr/src/sys/LQC/opt_global.h -I. -I@ -I@/contrib/altq -finline- limit=8000 --param inline-unit-growth=100 --param large-function-growth=1000 - fno-common -g -I/usr/obj/usr/src/sys/LQC -mno-align-long-strings -mpreferred- stack-boundary=2 -mno-mmx -mno-3dnow -mno-sse -mno-sse2 -mno-sse3 - ffreestanding -Wall -Wredundant-decls -Wnested-externs -Wstrict-prototypes - Wmissing-prototypes -Wpointer-arith -Winline -Wcast-qual -Wundef -Wno- pointer-sign -fformat-extensions -c /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c: In function 'coretemp_identify': /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c:98: error: 'cpu_vendor_id' undeclared (first use in this function) /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c:98: error: (Each undeclared identifier is reported only once /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c:98: error: for each function it appears in.) /usr/src/sys/modules/coretemp/../../dev/coretemp/coretemp.c:98: error: 'CPU_VENDOR_INTEL' undeclared (first use in this function) *** Error code 1 Stop in /usr/src/sys/modules/coretemp. *** Error code 1 Stop in /usr/src/sys/modules. *** Error code 1 Stop in /usr/obj/usr/src/sys/LQC. *** Error code 1 Stop in /usr/src. *** Error code 1 Stop in /usr/src. _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
