Author: cem
Date: Thu Nov 12 19:07:03 2015
New Revision: 290725
URL: https://svnweb.freebsd.org/changeset/base/290725
Log:
NTB: MFV 8b782fab: unify translation addresses
There is no need for the upstream and downstream addresses to be
different for the NTB configs. Go to using a single set of address. It
is still possible to configure them differently using module parameter
override however (CEM: tunable).
Authored by: Dave Jiang <dave.ji...@intel.com>
Reviewed by: Allen Hubbe <allen.hu...@emc.com>
Reviewed by: Jon Mason <jdma...@kudzu.us>
Obtained from: Linux (Dual BSD/GPL driver)
Sponsored by: EMC / Isilon Storage Division
Modified:
head/sys/dev/ntb/ntb_hw/ntb_hw.c
head/sys/dev/ntb/ntb_hw/ntb_regs.h
Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_hw.c Thu Nov 12 18:42:06 2015
(r290724)
+++ head/sys/dev/ntb/ntb_hw/ntb_hw.c Thu Nov 12 19:07:03 2015
(r290725)
@@ -415,19 +415,19 @@ static const struct ntb_xlat_reg xeon_se
};
static struct ntb_b2b_addr xeon_b2b_usd_addr = {
- .bar0_addr = XEON_B2B_BAR0_USD_ADDR,
- .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64,
- .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64,
- .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32,
- .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32,
+ .bar0_addr = XEON_B2B_BAR0_ADDR,
+ .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
+ .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
+ .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
+ .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
};
static struct ntb_b2b_addr xeon_b2b_dsd_addr = {
- .bar0_addr = XEON_B2B_BAR0_DSD_ADDR,
- .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64,
- .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64,
- .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32,
- .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32,
+ .bar0_addr = XEON_B2B_BAR0_ADDR,
+ .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
+ .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
+ .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
+ .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
};
SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0,
@@ -1346,18 +1346,18 @@ configure_atom_secondary_side_bars(struc
if (ntb->dev_type == NTB_DEV_USD) {
ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
- XEON_B2B_BAR2_DSD_ADDR64);
+ XEON_B2B_BAR2_ADDR64);
ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
- XEON_B2B_BAR4_DSD_ADDR64);
- ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64);
- ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64);
+ XEON_B2B_BAR4_ADDR64);
+ ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
+ ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
} else {
ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
- XEON_B2B_BAR2_USD_ADDR64);
+ XEON_B2B_BAR2_ADDR64);
ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
- XEON_B2B_BAR4_USD_ADDR64);
- ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64);
- ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64);
+ XEON_B2B_BAR4_ADDR64);
+ ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
+ ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
}
}
Modified: head/sys/dev/ntb/ntb_hw/ntb_regs.h
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_regs.h Thu Nov 12 18:42:06 2015
(r290724)
+++ head/sys/dev/ntb/ntb_hw/ntb_regs.h Thu Nov 12 19:07:03 2015
(r290725)
@@ -154,16 +154,11 @@
#define ATOM_PPD_DEV_TYPE 0x1000
/* All addresses are in low 32-bit space so 32-bit BARs can function */
-#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
-#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
-#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
-#define XEON_B2B_BAR4_USD_ADDR32 0x20000000ull
-#define XEON_B2B_BAR5_USD_ADDR32 0x40000000ull
-#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
-#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
-#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
-#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000ull
-#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000ull
+#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
+#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
+#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
+#define XEON_B2B_BAR4_ADDR32 0x20000000ull
+#define XEON_B2B_BAR5_ADDR32 0x40000000ull
/* The peer ntb secondary config space is 32KB fixed size */
#define XEON_B2B_MIN_SIZE 0x8000
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