Author: kib
Date: Sat Jun 13 07:31:50 2015
New Revision: 284338
URL: https://svnweb.freebsd.org/changeset/base/284338
Log:
MFC r284104:
Updates from SDM rev. 55.
Modified:
stable/10/sys/amd64/amd64/initcpu.c
stable/10/sys/amd64/include/md_var.h
stable/10/sys/i386/i386/initcpu.c
stable/10/sys/i386/include/md_var.h
stable/10/sys/x86/x86/identcpu.c
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/amd64/amd64/initcpu.c
==============================================================================
--- stable/10/sys/amd64/amd64/initcpu.c Sat Jun 13 06:09:00 2015
(r284337)
+++ stable/10/sys/amd64/amd64/initcpu.c Sat Jun 13 07:31:50 2015
(r284338)
@@ -74,6 +74,7 @@ u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
u_int cpu_clflush_line_size = 32;
u_int cpu_stdext_feature;
+u_int cpu_stdext_feature2;
u_int cpu_max_ext_state_size;
u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
Modified: stable/10/sys/amd64/include/md_var.h
==============================================================================
--- stable/10/sys/amd64/include/md_var.h Sat Jun 13 06:09:00 2015
(r284337)
+++ stable/10/sys/amd64/include/md_var.h Sat Jun 13 07:31:50 2015
(r284338)
@@ -49,6 +49,7 @@ extern u_int via_feature_rng;
extern u_int via_feature_xcrypt;
extern u_int cpu_clflush_line_size;
extern u_int cpu_stdext_feature;
+extern u_int cpu_stdext_feature2;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
Modified: stable/10/sys/i386/i386/initcpu.c
==============================================================================
--- stable/10/sys/i386/i386/initcpu.c Sat Jun 13 06:09:00 2015
(r284337)
+++ stable/10/sys/i386/i386/initcpu.c Sat Jun 13 07:31:50 2015
(r284338)
@@ -102,6 +102,7 @@ u_int cpu_mxcsr_mask; /* Valid bits in
#endif
u_int cpu_clflush_line_size = 32;
u_int cpu_stdext_feature;
+u_int cpu_stdext_feature2;
u_int cpu_max_ext_state_size;
u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
Modified: stable/10/sys/i386/include/md_var.h
==============================================================================
--- stable/10/sys/i386/include/md_var.h Sat Jun 13 06:09:00 2015
(r284337)
+++ stable/10/sys/i386/include/md_var.h Sat Jun 13 07:31:50 2015
(r284338)
@@ -49,6 +49,7 @@ extern u_int via_feature_rng;
extern u_int via_feature_xcrypt;
extern u_int cpu_clflush_line_size;
extern u_int cpu_stdext_feature;
+extern u_int cpu_stdext_feature2;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
Modified: stable/10/sys/x86/x86/identcpu.c
==============================================================================
--- stable/10/sys/x86/x86/identcpu.c Sat Jun 13 06:09:00 2015
(r284337)
+++ stable/10/sys/x86/x86/identcpu.c Sat Jun 13 07:31:50 2015
(r284338)
@@ -903,6 +903,9 @@ printcpuinfo(void)
"\013INVPCID"
/* Restricted Transactional Memory */
"\014RTM"
+ "\015PQM"
+ "\016NFPUSG"
+ "\020PQE"
/* Intel Memory Protection Extensions */
"\017MPX"
/* AVX512 Foundation */
@@ -922,6 +925,16 @@ printcpuinfo(void)
);
}
+ if (cpu_stdext_feature2 != 0) {
+ printf("\n Structured Extended Features2=0x%b",
+ cpu_stdext_feature2,
+ "\020"
+ "\001PREFETCHWT1"
+ "\004PKU"
+ "\005OSPKE"
+ );
+ }
+
if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
cpuid_count(0xd, 0x1, regs);
if (regs[0] != 0) {
@@ -1361,6 +1374,7 @@ identify_cpu(void)
cpu_stdext_disable = 0;
TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
cpu_stdext_feature &= ~cpu_stdext_disable;
+ cpu_stdext_feature2 = regs[2];
}
#ifdef __i386__
@@ -1705,18 +1719,39 @@ print_INTEL_TLB(u_int data)
case 0x8:
printf("1st-level instruction cache: 16 KB, 4-way set
associative, 32 byte line size\n");
break;
+ case 0x9:
+ printf("1st-level instruction cache: 32 KB, 4-way set
associative, 64 byte line size\n");
+ break;
case 0xa:
printf("1st-level data cache: 8 KB, 2-way set associative, 32
byte line size\n");
break;
+ case 0xb:
+ printf("Instruction TLB: 4 MByte pages, 4-way set associative,
4 entries\n");
+ break;
case 0xc:
printf("1st-level data cache: 16 KB, 4-way set associative, 32
byte line size\n");
break;
+ case 0xd:
+ printf("1st-level data cache: 16 KBytes, 4-way set associative,
64 byte line size");
+ break;
+ case 0xe:
+ printf("1st-level data cache: 24 KBytes, 6-way set associative,
64 byte line size\n");
+ break;
+ case 0x1d:
+ printf("2nd-level cache: 128 KBytes, 2-way set associative, 64
byte line size\n");
+ break;
+ case 0x21:
+ printf("2nd-level cache: 256 KBytes, 8-way set associative, 64
byte line size\n");
+ break;
case 0x22:
printf("3rd-level cache: 512 KB, 4-way set associative,
sectored cache, 64 byte line size\n");
break;
case 0x23:
printf("3rd-level cache: 1 MB, 8-way set associative, sectored
cache, 64 byte line size\n");
break;
+ case 0x24:
+ printf("2nd-level cache: 1 MBytes, 16-way set associative, 64
byte line size\n");
+ break;
case 0x25:
printf("3rd-level cache: 2 MB, 8-way set associative, sectored
cache, 64 byte line size\n");
break;
@@ -1729,13 +1764,13 @@ print_INTEL_TLB(u_int data)
case 0x30:
printf("1st-level instruction cache: 32 KB, 8-way set
associative, 64 byte line size\n");
break;
- case 0x39:
+ case 0x39: /* De-listed in SDM rev. 54 */
printf("2nd-level cache: 128 KB, 4-way set associative,
sectored cache, 64 byte line size\n");
break;
- case 0x3b:
+ case 0x3b: /* De-listed in SDM rev. 54 */
printf("2nd-level cache: 128 KB, 2-way set associative,
sectored cache, 64 byte line size\n");
break;
- case 0x3c:
+ case 0x3c: /* De-listed in SDM rev. 54 */
printf("2nd-level cache: 256 KB, 4-way set associative,
sectored cache, 64 byte line size\n");
break;
case 0x41:
@@ -1759,6 +1794,34 @@ print_INTEL_TLB(u_int data)
case 0x47:
printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte
line size\n");
break;
+ case 0x48:
+ printf("2nd-level cache: 3MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0x49:
+ if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
+ CPUID_TO_MODEL(cpu_id) == 0x6)
+ printf("3rd-level cache: 4MB, 16-way set associative,
64-byte line size\n");
+ else
+ printf("2nd-level cache: 4 MByte, 16-way set
associative, 64 byte line size");
+ break;
+ case 0x4a:
+ printf("3rd-level cache: 6MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0x4b:
+ printf("3rd-level cache: 8MByte, 16-way set associative, 64
byte line size\n");
+ break;
+ case 0x4c:
+ printf("3rd-level cache: 12MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0x4d:
+ printf("3rd-level cache: 16MByte, 16-way set associative, 64
byte line size\n");
+ break;
+ case 0x4e:
+ printf("2nd-level cache: 6MByte, 24-way set associative, 64
byte line size\n");
+ break;
+ case 0x4f:
+ printf("Instruction TLB: 4 KByte pages, 32 entries\n");
+ break;
case 0x50:
printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully
associative, 64 entries\n");
break;
@@ -1768,6 +1831,21 @@ print_INTEL_TLB(u_int data)
case 0x52:
printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully
associative, 256 entries\n");
break;
+ case 0x55:
+ printf("Instruction TLB: 2-MByte or 4-MByte pages, fully
associative, 7 entries\n");
+ break;
+ case 0x56:
+ printf("Data TLB0: 4 MByte pages, 4-way set associative, 16
entries\n");
+ break;
+ case 0x57:
+ printf("Data TLB0: 4 KByte pages, 4-way associative, 16
entries\n");
+ break;
+ case 0x59:
+ printf("Data TLB0: 4 KByte pages, fully associative, 16
entries\n");
+ break;
+ case 0x5a:
+ printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set
associative, 32 entries\n");
+ break;
case 0x5b:
printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64
entries\n");
break;
@@ -1780,6 +1858,12 @@ print_INTEL_TLB(u_int data)
case 0x60:
printf("1st-level data cache: 16 KB, 8-way set associative,
sectored cache, 64 byte line size\n");
break;
+ case 0x61:
+ printf("Instruction TLB: 4 KByte pages, fully associative, 48
entries\n");
+ break;
+ case 0x63:
+ printf("Data TLB: 1 GByte pages, 4-way set associative, 4
entries\n");
+ break;
case 0x66:
printf("1st-level data cache: 8 KB, 4-way set associative,
sectored cache, 64 byte line size\n");
break;
@@ -1798,6 +1882,9 @@ print_INTEL_TLB(u_int data)
case 0x72:
printf("Trace cache: 32K-uops, 8-way set associative\n");
break;
+ case 0x76:
+ printf("Instruction TLB: 2M/4M pages, fully associative, 8
entries\n");
+ break;
case 0x78:
printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte
line size\n");
break;
@@ -1819,6 +1906,9 @@ print_INTEL_TLB(u_int data)
case 0x7f:
printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte
line size\n");
break;
+ case 0x80:
+ printf("2nd-level cache: 512 KByte, 8-way set associative,
64-byte line size\n");
+ break;
case 0x82:
printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte
line size\n");
break;
@@ -1837,12 +1927,99 @@ print_INTEL_TLB(u_int data)
case 0x87:
printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte
line size\n");
break;
+ case 0xa0:
+ printf("DTLB: 4k pages, fully associative, 32 entries\n");
+ break;
case 0xb0:
printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128
entries\n");
break;
+ case 0xb1:
+ printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M
pages, 4-way, 4 entries\n");
+ break;
+ case 0xb2:
+ printf("Instruction TLB: 4KByte pages, 4-way set associative,
64 entries\n");
+ break;
case 0xb3:
printf("Data TLB: 4 KB Pages, 4-way set associative, 128
entries\n");
break;
+ case 0xb4:
+ printf("Data TLB1: 4 KByte pages, 4-way associative, 256
entries\n");
+ break;
+ case 0xb5:
+ printf("Instruction TLB: 4KByte pages, 8-way set associative,
64 entries\n");
+ break;
+ case 0xb6:
+ printf("Instruction TLB: 4KByte pages, 8-way set associative,
128 entries\n");
+ break;
+ case 0xba:
+ printf("Data TLB1: 4 KByte pages, 4-way associative, 64
entries\n");
+ break;
+ case 0xc0:
+ printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative,
8 entries\n");
+ break;
+ case 0xc1:
+ printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way
associative, 1024 entries\n");
+ break;
+ case 0xc2:
+ printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16
entries\n");
+ break;
+ case 0xc3:
+ printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way
associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
+ break;
+ case 0xca:
+ printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative,
512 entries\n");
+ break;
+ case 0xd0:
+ printf("3rd-level cache: 512 KByte, 4-way set associative, 64
byte line size\n");
+ break;
+ case 0xd1:
+ printf("3rd-level cache: 1 MByte, 4-way set associative, 64
byte line size\n");
+ break;
+ case 0xd2:
+ printf("3rd-level cache: 2 MByte, 4-way set associative, 64
byte line size\n");
+ break;
+ case 0xd6:
+ printf("3rd-level cache: 1 MByte, 8-way set associative, 64
byte line size\n");
+ break;
+ case 0xd7:
+ printf("3rd-level cache: 2 MByte, 8-way set associative, 64
byte line size\n");
+ break;
+ case 0xd8:
+ printf("3rd-level cache: 4 MByte, 8-way set associative, 64
byte line size\n");
+ break;
+ case 0xdc:
+ printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0xdd:
+ printf("3rd-level cache: 3 MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0xde:
+ printf("3rd-level cache: 6 MByte, 12-way set associative, 64
byte line size\n");
+ break;
+ case 0xe2:
+ printf("3rd-level cache: 2 MByte, 16-way set associative, 64
byte line size\n");
+ break;
+ case 0xe3:
+ printf("3rd-level cache: 4 MByte, 16-way set associative, 64
byte line size\n");
+ break;
+ case 0xe4:
+ printf("3rd-level cache: 8 MByte, 16-way set associative, 64
byte line size\n");
+ break;
+ case 0xea:
+ printf("3rd-level cache: 12MByte, 24-way set associative, 64
byte line size\n");
+ break;
+ case 0xeb:
+ printf("3rd-level cache: 18MByte, 24-way set associative, 64
byte line size\n");
+ break;
+ case 0xec:
+ printf("3rd-level cache: 24MByte, 24-way set associative, 64
byte line size\n");
+ break;
+ case 0xf0:
+ printf("64-Byte prefetching\n");
+ break;
+ case 0xf1:
+ printf("128-Byte prefetching\n");
+ break;
}
}
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