Author: jhb
Date: Tue May 26 15:33:34 2009
New Revision: 192813
URL: http://svn.freebsd.org/changeset/base/192813
Log:
MFC: Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same
name.
Modified:
stable/7/sys/ (props changed)
stable/7/sys/amd64/pci/pci_cfgreg.c
stable/7/sys/contrib/pf/ (props changed)
stable/7/sys/dev/ath/ath_hal/ (props changed)
stable/7/sys/dev/cxgb/ (props changed)
stable/7/sys/i386/pci/pci_cfgreg.c
Modified: stable/7/sys/amd64/pci/pci_cfgreg.c
==============================================================================
--- stable/7/sys/amd64/pci/pci_cfgreg.c Tue May 26 15:30:32 2009
(r192812)
+++ stable/7/sys/amd64/pci/pci_cfgreg.c Tue May 26 15:33:34 2009
(r192813)
@@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
#include <sys/lock.h>
#include <sys/kernel.h>
#include <sys/mutex.h>
+#include <sys/sysctl.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <vm/vm.h>
@@ -56,6 +57,8 @@ static void pciereg_cfgwrite(int bus, un
static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data,
int bytes);
+SYSCTL_DECL(_hw_pci);
+
static int cfgmech;
static vm_offset_t pcie_base;
static int pcie_minbus, pcie_maxbus;
@@ -63,6 +66,8 @@ static uint32_t pcie_badslots;
static struct mtx pcicfg_mtx;
static int mcfg_enable = 0;
TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
+SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
+ "Enable support for PCI-e memory mapped config access");
/*
* Initialise access to PCI configuration space
Modified: stable/7/sys/i386/pci/pci_cfgreg.c
==============================================================================
--- stable/7/sys/i386/pci/pci_cfgreg.c Tue May 26 15:30:32 2009
(r192812)
+++ stable/7/sys/i386/pci/pci_cfgreg.c Tue May 26 15:33:34 2009
(r192813)
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
#include <sys/mutex.h>
#include <sys/malloc.h>
#include <sys/queue.h>
+#include <sys/sysctl.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <machine/pci_cfgreg.h>
@@ -75,6 +76,8 @@ enum {
CFGMECH_PCIE,
};
+SYSCTL_DECL(_hw_pci);
+
static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
static uint64_t pcie_base;
static int pcie_minbus, pcie_maxbus;
@@ -84,6 +87,8 @@ static int devmax;
static struct mtx pcicfg_mtx;
static int mcfg_enable = 0;
TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
+SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
+ "Enable support for PCI-e memory mapped config access");
static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
int bytes);
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