Author: yongari
Date: Wed Dec  3 08:56:01 2008
New Revision: 185576
URL: http://svn.freebsd.org/changeset/base/185576

Log:
  Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT
  power adjustment. This change is required to guarantee correct
  operation on certain switches.
  
  Submitted by: Jie Yang < Jie.Yang <> Atheros com >

Modified:
  head/sys/dev/ale/if_ale.c

Modified: head/sys/dev/ale/if_ale.c
==============================================================================
--- head/sys/dev/ale/if_ale.c   Wed Dec  3 03:20:18 2008        (r185575)
+++ head/sys/dev/ale/if_ale.c   Wed Dec  3 08:56:01 2008        (r185576)
@@ -385,6 +385,39 @@ ale_phy_reset(struct ale_softc *sc)
            GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
            GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
        DELAY(1000);
+
+#define        ATPHY_DBG_ADDR          0x1D
+#define        ATPHY_DBG_DATA          0x1E
+
+       /* Enable hibernation mode. */
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x0B);
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_DATA, 0xBC00);
+       /* Set Class A/B for all modes. */
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x00);
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_DATA, 0x02EF);
+       /* Enable 10BT power saving. */
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x12);
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_DATA, 0x4C04);
+       /* Adjust 1000T power. */
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x04);
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x8BBB);
+       /* 10BT center tap voltage. */
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x05);
+       ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
+           ATPHY_DBG_ADDR, 0x2C46);
+
+#undef ATPHY_DBG_ADDR
+#undef ATPHY_DBG_DATA
+       DELAY(1000);
 }
 
 static int
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