Module Name: src
Committed By: maxv
Date: Sat Jun 16 17:11:13 UTC 2018
Modified Files:
src/sys/arch/x86/x86: fpu.c x86_machdep.c
Log Message:
Need IPIs when enabling eager fpu switch, to clear each fpu and get us
started. Otherwise it is possible that the first context switch on one of
the cpus will restore an invalid fpu state in the new lwp, if that lwp
had its fpu state stored on another cpu that didn't have time to do an
fpu save since eager-fpu was enabled.
Use barriers and all the related crap. The point is that we want to
ensure that no context switch occurs between [each fpu is cleared] and
[x86_fpu_eager is set to 'true'].
Also add KASSERTs.
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/x86/x86/fpu.c
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/x86/x86/x86_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
