Module Name: src
Committed By: martin
Date: Fri Mar 16 13:05:32 UTC 2018
Modified Files:
src/sys/arch/x86/include [netbsd-8]: cacheinfo.h specialreg.h
src/sys/arch/x86/x86 [netbsd-8]: identcpu.c
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #633):
sys/arch/x86/include/specialreg.h: revision 1.107
sys/arch/x86/include/specialreg.h: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.109
sys/arch/x86/include/cacheinfo.h: revision 1.23
sys/arch/x86/include/specialreg.h: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.111
sys/arch/x86/include/specialreg.h: revision 1.112
sys/arch/x86/include/specialreg.h: revision 1.113
sys/arch/x86/include/specialreg.h: revision 1.114
usr.sbin/cpuctl/arch/i386.c: revision 1.79
sys/arch/x86/x86/identcpu.c: revision 1.70
sys/arch/x86/include/specialreg.h: revision 1.106
Add comment.
Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.
Print Intel cpuid 7 %edx.
Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>
fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
Add MSR_IA32_ARCH_CAPABILITIES definition.
Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.
Sort entries. No functional change.
s/CLFUSH/CLFLUSH/
No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.22.10.1 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.98.2.1 -r1.98.2.2 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.55.2.1 -r1.55.2.2 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.74.6.1 -r1.74.6.2 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
