Module Name: src
Committed By: snj
Date: Mon Feb 12 18:42:16 UTC 2018
Modified Files:
src/sys/arch/sparc/sparc [netbsd-7-0]: timer.c timer_sun4m.c timerreg.h
Log Message:
Pull up following revision(s) (requested by mrg in ticket #1552):
sys/arch/sparc/sparc/timer.c: 1.33-1.34
sys/arch/sparc/sparc/timer_sun4m.c: 1.31
sys/arch/sparc/sparc/timerreg.h: 1.10
fix time goes backwards problems on sparc.
there are a few things here:
- there's a race between reading the limit register (which clears
the interrupt and the limit bit) and increasing the latest offset.
this can happen easily if an interrupt comes between the read and
the call to tickle_tc() that increases the offset (i obverved this
actually happening.)
- in early boot, sometimes the counter can cycle twice before the
tickle happens.
to handle these issues, add two workarounds:
- if the limit bit isn't set, but the counter value is less than
the previous value, and the offset hasn't changed, use the same
fixup as if the limit bit was set. this handles the first case
above.
- add a hard-workaround for never allowing returning a smaller
value (except during 32 bit overflow): if the result is less than
the last result, add fixups until it does (or until it would
overflow.)
the first workaround fixes general run-time issues, and the second
fixes issues only seen during boot.
also expand some comments in timer_sun4m.c and re-enable the sun4m
sub-microsecond tmr_ustolim4m() support (but it's always called with
at least 'tick' microseconds, so the end result is the same.)
--
fix hang at 4B microseconds (1h12 or so), and simplify part of the previous
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.32.8.1 src/sys/arch/sparc/sparc/timer.c
cvs rdiff -u -r1.30 -r1.30.8.1 src/sys/arch/sparc/sparc/timer_sun4m.c
cvs rdiff -u -r1.9 -r1.9.144.1 src/sys/arch/sparc/sparc/timerreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
