Module Name: src Committed By: chs Date: Mon Feb 27 06:56:33 UTC 2017
Modified Files:
src/sys/arch/mips/mips: db_disasm.c
Log Message:
the second operand to cfc1/ctc1 isn't an FPU data register
so don't make it look like one.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/mips/mips/db_disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
