Module Name: src
Committed By: chs
Date: Mon Feb 27 06:54:00 UTC 2017
Modified Files:
src/lib/libc/arch/powerpc/gen: fpsetmask.c
src/sys/arch/powerpc/include: instr.h
src/sys/arch/powerpc/powerpc: trap.c
Log Message:
have fpsetmask() change the FE0/FE1 MSR bits to precise mode if any
FP exceptions are enabled. fix the kernel emulation of mfmsr and mtmsr
to use the correct opcodes for these instructions. ignore PSL_FE
(the FP enable bit) in the MSR that a user program tries to set,
since it will naturally be set for FP-using processes but
we can't let the user process manage that bit.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/lib/libc/arch/powerpc/gen/fpsetmask.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/powerpc/include/instr.h
cvs rdiff -u -r1.150 -r1.151 src/sys/arch/powerpc/powerpc/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
