Module Name: src
Committed By: snj
Date: Wed Jun 22 08:26:05 UTC 2016
Modified Files:
src/sys/arch/arm/allwinner [netbsd-7]: files.awin
src/sys/conf [netbsd-7]: files
src/sys/dev/ic [netbsd-7]: com.c comreg.h comvar.h ns16550reg.h
Log Message:
Pull up following revision(s) (requested by bouyer in ticket #1178):
sys/arch/arm/allwinner/files.awin: revision 1.36
sys/conf/files: revision 1.1159
sys/dev/ic/com.c: revision 1.339
sys/dev/ic/comreg.h: revision 1.25
sys/dev/ic/comvar.h: revision 1.82
sys/dev/ic/ns16550reg.h: revision 1.11
The UART in the allwiner SoCs is not full-compatible with the 16550, and
it's not a 16750 either. Like the 16750 it has the IIR_BUSY interrupt,
which is triggered when writing to LCR while the chip
can't accept it. But unlike the 16750, it has a specific register,
HALT, to allow writing to the LCR and divisor registers, and then
commit the changes.
Tested on an A20 SoC, changing the baud rate while keeping the
tty device open and incoming data.
To generate a diff of this commit:
cvs rdiff -u -r1.8.10.4 -r1.8.10.5 src/sys/arch/arm/allwinner/files.awin
cvs rdiff -u -r1.1096.2.6 -r1.1096.2.7 src/sys/conf/files
cvs rdiff -u -r1.327 -r1.327.2.1 src/sys/dev/ic/com.c
cvs rdiff -u -r1.22 -r1.22.4.1 src/sys/dev/ic/comreg.h
cvs rdiff -u -r1.78 -r1.78.4.1 src/sys/dev/ic/comvar.h
cvs rdiff -u -r1.10 -r1.10.4.1 src/sys/dev/ic/ns16550reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
