Module Name: src
Committed By: skrll
Date: Sun Feb 14 10:48:08 UTC 2016
Update of /cvsroot/src/sys/external/bsd/dwc2/dist
In directory ivanova.netbsd.org:/tmp/cvs-serv16576
Log Message:
Import latest dwc2 sources
commit 192cb07f7928e8cb09a9851e6c0f7478baa3bc6d
Author: John Youn <john.y...@synopsys.com>
Date: Mon Jan 11 16:32:28 2016 -0800
usb: dwc2: Fix probe problem on bcm2835
Fixes an issue found on Raspberry PI platform that prevents probe. Don't
skip setting the force mode if it's already set.
Fixes: 09c96980dc72 ("usb: dwc2: Add functions to set and clear force mode")
Tested-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Reported-by: Stefan Wahren <stefan.wah...@i2se.com>
Reported-by: Remi Pommarel <r...@triplefau.lt>
Tested-by: Stefan Wahren <stefan.wah...@i2se.com>
Tested-by: Remi Pommarel <r...@triplefau.lt>
Signed-off-by: Felipe Balbi <ba...@kernel.org>
commit 03b32e4c9bd1b52fcf1e4304e7a704aa0315e398
Author: John Youn <john.y...@synopsys.com>
Date: Mon Jan 11 16:32:14 2016 -0800
Revert "usb: dwc2: Move reset into dwc2_get_hwparams()"
This reverts commit 263b7fb557f7 ("usb: dwc2: Move reset into
dwc2_get_hwparams()") due to regression found on bcm2835 platform. USB
ethernet fails, due to being unable to pick up proper parameters when
performing a plain reset before reading hw params.
Below shows the results of the gnptxfsiz and hptxfsiz with and before
and after reverting this (from Stefan Wahren):
So here is the probe result before Patch 1 is applied:
[ 1.283148] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to
host
[ 1.313894] dwc2 20980000.usb: gnptxfsiz=00201000
[ 1.314104] dwc2 20980000.usb: hptxfsiz=00000000
[ 1.353908] dwc2 20980000.usb: 256 invalid for host_nperio_tx_fifo_size.
Check HW configuration.
[ 1.354262] dwc2 20980000.usb: 512 invalid for host_perio_tx_fifo_size.
Check HW configuration.
[ 1.394249] dwc2 20980000.usb: DWC OTG Controller
[ 1.394561] dwc2 20980000.usb: new USB bus registered, assigned bus
number 1
[ 1.394917] dwc2 20980000.usb: irq 33, io mem 0x00000000
And here is the probe result after Patch 1 is applied:
[ 1.280107] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to
host
[ 1.353949] dwc2 20980000.usb: gnptxfsiz=01001000
[ 1.354166] dwc2 20980000.usb: hptxfsiz=02002000
[ 1.434301] dwc2 20980000.usb: DWC OTG Controller
[ 1.434616] dwc2 20980000.usb: new USB bus registered, assigned bus
number 1
[ 1.434973] dwc2 20980000.usb: irq 33, io mem 0x00000000
Tested-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Reported-by: Stefan Wahren <stefan.wah...@i2se.com>
Reported-by: Remi Pommarel <r...@triplefau.lt>
Tested-by: Stefan Wahren <stefan.wah...@i2se.com>
Tested-by: Remi Pommarel <r...@triplefau.lt>
Signed-off-by: Felipe Balbi <ba...@kernel.org>
commit a40a00318c7fcdd23e73cfffac0e33430a43a3e3
Author: Heiko Stübner <heiko.stueb...@collabora.com>
Date: Fri Dec 18 19:30:59 2015 +0100
usb: dwc2: add shutdown callback to platform variant
In specific conditions (involving usb hubs) dwc2 devices can create a
lot of interrupts, even to the point of overwhelming devices running
at low frequencies. Some devices need to do special clock handling
at shutdown-time which may bring the system clock below the threshold
of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
in a shutdown callbacks prevents reboots/poweroffs from getting stuck
in such cases.
The hsotg struct already contains an unused irq element, so we can
just use it to store the irq number for the shutdown callback.
Reviewed-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Heiko Stuebner <heiko.stueb...@collabora.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 6d76c92c2fcbee4fd1f6d7b375d71057c7a615b1
Author: Marek Vasut <ma...@denx.de>
Date: Fri Dec 18 03:26:17 2015 +0100
usb: dwc2: gadget: Repair DSTS register decoding
The "enumspd" field is located in register DSTS[2:1], but the code
which checks the bitfield does not shift the value accordingly. This
in turn causes incorrect detection of gadget link partner speed in
dwc2_hsotg_irq_enumdone() .
Shift the value accordingly to fix the problem with speed detection.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Felipe Balbi <ba...@ti.com>
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Cc: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 60c0288c72c980fb37ed4e48f68c9743a53b662c
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:18:41 2015 -0800
usb: dwc2: gadget: Remove call to dwc2_hsotg_init()
Remove call to dwc2_hsotg_init() from dwc2_gadget_init(). The
gadget_init function should not access any device registers because the
mode isn't guaranteed here.
Also, this is already called elsewhere before anything starts on the
gadget so it is not necessary here.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 25362d318371e1e271dda24995ceabb8457b3b7c
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:18:27 2015 -0800
usb: dwc2: Remove redundant reset in probe
Reset already happens before this so just force the dr_mode.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 97e463886b873f62bea2293e7edf81fdb884b84f
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:18:13 2015 -0800
usb: dwc2: Reduce delay when forcing mode in reset
The delay for force mode is only 25ms according to the databook.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 241729baa932a69cd203dbaa81abbb8af5b77b65
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:17:59 2015 -0800
usb: dwc2: gadget: Replace dwc2_hsotg_corereset()
The dwc2_core_reset() function exists in the core so use that one
instead.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 43e9034904dd37db7ed87fa8f5039c561c4004cd
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:17:45 2015 -0800
usb: dwc2: gadget: Use hw params from core
Use the previously cached hw params in the gadget. This saves a reset
and force mode in the gadget initialization during probe and makes
getting the hardware parameters consistent between gadget and host.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 55e1040e424b59063da627fb580ec953f4c01de7
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:17:31 2015 -0800
usb: dwc2: Improve handling of host and device hwparams
Adds separate functions to get the host and device specific hardware
parameters. The functions check whether the parameters need to be read
at all, depending on dr_mode, and forces the mode only if necessary.
This saves some delays during probe. This also adds two device mode
parameters that will be used by the gadget.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 09c96980dc723462ed2eeacc945fed5bcb278f85
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:17:12 2015 -0800
usb: dwc2: Add functions to set and clear force mode
Added functions to set force mode for host and device. These functions
will check the current mode and only force if needed thus avoiding
unnecessary force mode delays. However clearing the mode is currently
done unconditionally and with the delay in place. This is needed during
the connector ID status change interrupt in order to ensure that the
mode has changed properly. This preserves the old behavior only for this
case. The warning comment about this is moved into the clear mode
condition.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 263b7fb557f797d9d4d1dcf93fb6bb2efc3f1d46
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:16:58 2015 -0800
usb: dwc2: Move reset into dwc2_get_hwparams()
The reset is required to get reset values of the hardware parameters but
the force mode is not. Move the base reset into dwc2_get_hwparams() and
do the reset and force mode afterwards.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 1696d5ab99ef885ae62da5ad58f9eff16da7ff78
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:16:45 2015 -0800
usb: dwc2: Move mode querying functions into core.h
These functions should go in core.h where they can be called from core,
device, or host.
Signed-off-by: John Youn <johny...@synopsys.com>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 5268ed9d2e3b52f703f3661eef14cecbb2b572d4
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:16:31 2015 -0800
usb: dwc2: Fix dr_mode validation
The dr_mode parameter was being checked against how the dwc2 module
was being configured at compile time. But it wasn't checked against
the hardware capabilities, nor were the hardware capabilities checked
against the compilation parameters.
This commit adds those checks and adjusts dr_mode to an appropriate
value, if needed. If the hardware capabilities and module compilation
do not match then we fail as it wouldn't be possible to run properly.
The hardware, module, and dr_mode, can each be set to host, device,
or otg. Check that all these values are compatible and adjust the
value of dr_mode if possible.
The following table summarizes the behavior:
actual
HW MOD dr_mode dr_mode
------------------------------
HST HST any : HST
HST DEV any : ---
HST OTG any : HST
DEV HST any : ---
DEV DEV any : DEV
DEV OTG any : DEV
OTG HST any : HST
OTG DEV any : DEV
OTG OTG any : dr_mode
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 6bea962053e76a4407f0d138184a8737eea960ee
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:16:17 2015 -0800
usb: dwc2: Add functions to check the HW OTG config
Added functions to query the GHWCFG2.OTG_MODE. This tells us whether the
controller hardware is configured for OTG, device-only, or host-only.
Signed-off-by: John Youn <johny...@synopsys.com>
Tested-by: Douglas Anderson <diand...@chromium.org>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit b5d308abef1c5c0f24128845e41d414a8f8438f6
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:16:03 2015 -0800
usb: dwc2: Add dwc2_core_reset()
dwc2_core_reset() was previously renamed to
dwc2_core_reset_and_dr_force_mode(). Now add back dwc2_core_reset() which
performs only a basic core reset without forcing the mode.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 6d58f346a61ff50eda740e6216e9829e572d75c8
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:15:49 2015 -0800
usb: dwc2: Rename dwc2_core_reset()
Renamed dwc2_core_reset() to dwc2_core_reset_and_force_dr_mode(). This
describes what it is doing more accurately. This is in preparation of
introducing a plain dwc2_core_reset() function that only performs the
reset and doesn't force the mode.
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit b8ccc593eeeacde0e6794c4dcec0a57eba7356e6
Author: John Youn <john.y...@synopsys.com>
Date: Thu Dec 17 11:15:35 2015 -0800
usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()
According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.
Signed-off-by: John Youn <johny...@synopsys.com>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 7d56cc2620f523eba7a831daa22186c8ae5bbdfe
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Dec 17 11:15:21 2015 -0800
usb: dwc2: Avoid more calls to dwc2_core_reset()
Calls to dwc2_core_reset() are currently very slow, taking at least
150ms (possibly more). It behooves us to take as many of these calls
out as possible.
It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init()
should (as documented in the code) only be needed if we need to do a PHY
SELECT. That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.
This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 20bde643434d541bc5f662c5836a05e9e276eca3
Author: Yunzhi Li <l...@rock-chips.com>
Date: Thu Dec 17 11:15:08 2015 -0800
usb: dwc2: reduce dwc2 driver probe time
I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.
This patch trying to reduce unnecessary delay time.
In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.
And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?
It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?
I have tried this patch in my RK3288-evb board. It works well.
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit f619473140df4e1a10f4c10f693d214807ebdb03
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Dec 17 11:14:54 2015 -0800
usb: dwc2: Speed dwc2_get_hwparams() on some host-only ports
On some host-only DWC2 ports (like the one in rk3288) when we set
GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the
bit set. Presumably that's because the port is always forced to HOST
mode so there's no reason to implement these status bits.
Since we know dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 0fe239bc190453fe82252c6d41a74e685730cd93
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Dec 17 11:14:40 2015 -0800
usb: dwc2: Avoid double-reset at boot time
In (usb: dwc2: reset dwc2 core before dwc2_get_hwparams()) we added an
extra reset to the probe path for the dwc2 USB controllers. This
allowed proper detection of parameters even if the firmware had already
used the USB part.
Unfortunately, this extra reset is quite slow and is affecting boot
speed. We can avoid the double-reset by skipping the extra reset that
would happen just after the one we added. Logic that explains why this
is safe:
* As of the CL mentioned above, we now always call dwc2_core_reset() in
dwc2_driver_probe() before dwc2_hcd_init().
* The only caller of dwc2_hcd_init() is dwc2_driver_probe(), so we're
guaranteed that dwc2_core_reset() was called before dwc2_hdc_init().
* dwc2_hdc_init() is the only caller that passes an irq other than -1 to
dwc2_core_init(). Thus if dwc2_core_init() is called with an irq
other than -1 we're guaranteed that dwc2_core_reset was called before
dwc2_core_init().
...this allows us to remove the dwc2_core_reset() in dwc2_core_init() if
irq is not < 0.
Note that since "irq" wasn't used in the function dwc2_core_init()
anyway and since select_phy was always set at exactly the same times we
could avoid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit cebfdbf329ae929ccb71632888a7c2100c3d1eeb
Author: Yunzhi Li <l...@rock-chips.com>
Date: Thu Dec 17 11:14:26 2015 -0800
usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[ 2.074764] dwc2 ff580000.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 991824677fe0a555394d8093b64647dbd08b89b0
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Dec 17 11:14:12 2015 -0800
usb: dwc2: Restore GUSBCFG in dwc2_get_hwparams()
Previously dwc2_get_hwparams() was changing GUSBCFG and not putting it
back the way it was (specifically it set and cleared FORCEHOSTMODE).
Since we want to move dwc2_core_reset() _before_ dwc2_get_hwparams() we
should make sure dwc2_get_hwparams() isn't messing with things in a
permanent way.
Since we're now looking at GUSBCFG, it's obvious that we shouldn't need
all the extra delays if FORCEHOSTMODE was already set. This will avoid
some delays for any ports that have forced host mode.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 3be99cd0e882dd2127b8cfe3942f5e464915aeba
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Mon Dec 7 12:07:31 2015 +0100
usb: dwc2: gadget: don't overwrite DCTL register on NAKEFF interrupts
When receiving GINTSTS_GINNAKEFF or GINTSTS_GOUTNAKEFF interrupt,
DCTL will be overwritten with DCTL_CGOUTNAK or DCTL_CGNPINNAK values.
Instead of overwriting it, write only needed bits.
It could cause an issue if GINTSTS_GINNAKEFF or GINTSTS_GOUTNAKEFF
interrupt is received after dwc2 disabled pullup by writing
DCTL_SFTDISCON bit.
Pullup will then be re-enabled whereas it should not.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 0676c7e734e3807f4e91f5d0edcaeed1f5ff412a
Author: Du, Changbin <changbin...@intel.com>
Date: Fri Dec 4 15:38:23 2015 +0800
usb: dwc2: fix transfer stop programming for out endpoint
To stop an out endpoint, software should set sets the Global OUT NAK,
but not the Global Non-periodic IN NAK. This driver bug leads the out-ep
failed be in disabled state with below error.
dwc2_hsotg_ep_stop_xfr: timeout DOEPCTL.EPDisable
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Du, Changbin <changbin...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 29539019b46f0e5f64f80f2e9dc8f9bb34d16b4b
Author: Douglas Anderson <diand...@chromium.org>
Date: Fri Nov 20 09:06:28 2015 -0800
usb: dwc2: host: Clear interrupts before handling them
In general it is wise to clear interrupts before processing them. If
you don't do that, you can get:
1. Interrupt happens
2. You look at system state and process interrupt
3. A new interrupt happens
4. You clear interrupt without processing it.
This patch was actually a first attempt to fix missing device insertions
as described in (usb: dwc2: host: Fix missing device insertions) and it
did solve some of the signal bouncing problems but not all of
them (which is why I submitted the other patch). Specifically, this
patch itself would sometimes change:
1. hardware sees connect
2. hardware sees disconnect
3. hardware sees connect
4. dwc2_port_intr() - clears connect interrupt
5. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect()
...to:
1. hardware sees connect
2. hardware sees disconnect
3. dwc2_port_intr() - clears connect interrupt
4. hardware sees connect
5. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect()
...but with different timing then sometimes we'd still miss cable
insertions.
In any case, though this patch doesn't fix any (known) problems, it
still seems wise as a general policy to clear interrupt before handling
them.
Note that for dwc2_handle_usb_port_intr(), instead of moving the clear
of PRTINT to the beginning of the function we remove it completely. The
only way to clear PRTINT is to clear the sources that set it in the
first place.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 4a065c7bdbec9536f7b899241b125b9c3b5ba97a
Author: Douglas Anderson <diand...@chromium.org>
Date: Fri Nov 20 09:06:27 2015 -0800
usb: dwc2: host: Add missing spinlock in dwc2_hcd_reset_func()
The dwc2_hcd_reset_func() function is only ever called directly by a
delayed work function. As such no locks are already held when the
function is called.
Doing a read-modify-write of CPU registers and setting fields in the
main hsotg data structure is a bad idea without locks. Let's add
locks.
The bug was found by code inspection only. It turns out that the
dwc2_hcd_reset_func() is only ever called today if the
"host_support_fs_ls_low_power" parameter is enabled and no code in
mainline enables that parameter. Thus no known issues in mainline are
fixed by this patch, but it's still probably wise to fix the function.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 69b76cdff592058ea445cd40e18c75dffaba4cb9
Author: Douglas Anderson <diand...@chromium.org>
Date: Wed Nov 11 10:33:52 2015 -0800
usb: dwc2: host: Support immediate retries for split transactions
In some cases, like when you've got a "Microsoft Wireless Keyboard 2000"
connected to dwc2 with a hub, expected that we'll get some transfer
errors sometimes. The controller is expected to try at least 3 times
before giving up. See figure "Figure A-67. Normal HS CSPLIT 3 Strikes
Smash" in the USB spec.
The dwc2 controller has a way to support this by using the "EC_MC"
field. The Raspberry Pi driver has logic for setting this right. See
fiq_fsm_queue_split_transaction() in their "dwc_otg_hcd.c". Let's use
the same logic.
After making this change, we no longer get dropped characters from the
above mentioned keyboard. Other devices on the same bus as the keyboard
also behave more properly.
Thanks for Julius Werner for the expert analysis and suggestions.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 6a6595318ac2dd169d2931a1d9431a64f4ada75c
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Nov 19 13:23:14 2015 -0800
usb: dwc2: host: Fix missing device insertions
If you've got your interrupt signals bouncing a bit as you insert your
USB device, you might end up in a state when the device is connected but
the driver doesn't know it.
Specifically, the observed order is:
1. hardware sees connect
2. hardware sees disconnect
3. hardware sees connect
4. dwc2_port_intr() - clears connect interrupt
5. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect()
Now you'll be stuck with the cable plugged in and no further interrupts
coming in but the driver will think we're disconnected.
We'll fix this by checking for the missing connect interrupt and
re-connecting after the disconnect is posted. We don't skip the
disconnect because if there is a transitory disconnect we really want to
de-enumerate and re-enumerate.
Notes:
1. As part of this change we add a "force" parameter to
dwc2_hcd_disconnect() so that when we're unloading the module we
avoid the new behavior. The need for this was pointed out by John
Youn.
2. The bit of code needed at the end of dwc2_hcd_disconnect() is
exactly the same bit of code from dwc2_port_intr(). To avoid
duplication, we refactor that code out into a new function
dwc2_hcd_connect().
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 37dd9d65cc41fcc7e77645a1cdf2659472809b96
Author: Zhangfei Gao <zhangfei....@linaro.org>
Date: Wed Nov 18 15:39:47 2015 +0800
usb: dwc2: add support of hi6220
Support hisilicon,hi6220-usb for HiKey board
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Zhangfei Gao <zhangfei....@linaro.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 3b5fcc9ac2f4453a5609cc89ac7618b1b27ccb01
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Fri Nov 20 11:49:31 2015 +0100
usb: dwc2: host: use kmem cache to allocate descriptors
Kmem caches help to get correct boundary for descriptor buffers
which need to be 512 bytes aligned for dwc2 controller.
Two kmem caches are needed for generic descriptors and for
hs isochronous descriptors which doesn't have same size.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit e23b8a54a440a2b8ee5c9dc3eb2099ecf813ef70
Author: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Date: Fri Nov 20 11:49:30 2015 +0100
usb: dwc2: host: fix descriptor list address masking
Masks for HCDMA.CTD and HCDMA.DMAAddr are incorrect. As we always
start from first descriptor, no need to mask the address anyway.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 95105a998dff0747327f11708ea24480ee0eca54
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Fri Nov 20 11:49:29 2015 +0100
usb: dwc2: host: avoid usage of dma_alloc_coherent with irqs disabled
Use Streaming DMA mappings to handle cache coherency of frame list and
descriptor list. Cache are always flushed before controller access it
or before cpu access it.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit fbb9e22b15ad3c9a98c66bad801b4d1366e8bf20
Author: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Date: Fri Nov 20 11:49:28 2015 +0100
usb: dwc2: host: enable descriptor dma for fs devices
As descriptor dma mode does not support split transfers, it can't be
enabled for high speed devices. Add a core parameter to enable it for
full speed devices.
Ensure frame list and descriptor list are correctly freed during
disconnect.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 762d3a1a9cd7438a8453e005ee5b2bab3203d9c3
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:45 2015 +0100
usb: dwc2: host: process all completed urbs
Process all completed urbs, if more urbs are complete by the time
driver processes completion interrupt.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 3f808bdae75eaf464b1b2710894950772a3784f8
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:44 2015 +0100
usb: dwc2: host: always increment available host channel during release
When releasing a channel, increment hsotg->available_host_channels even
in case a periodic channel is released.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit c17b337c1ea4c681595531912585a94f4bd7f8e7
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:43 2015 +0100
usb: dwc2: host: program descriptor for next frame
Isochronous descriptor is currently programmed for the frame
after the last descriptor was programmed.
If the last descriptor frame underrun, then current descriptor must
take this into account and must be programmed on the current frame + 1.
This overrun usually happens when system is loaded and dwc2 can't init
descriptor list in time.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit b9392d9920fdce50abbe4af758cd1a24b922c81c
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:42 2015 +0100
usb: dwc2: host: add function to compare frame index
This function allow comparing frame index used for
descriptor list which has 64 entries.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 2b046bc5aaefd4aba7195e6a73afe14f7f786692
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:41 2015 +0100
usb: dwc2: host: spinlock release channel
Prevent dwc2 driver from accessing channel while it frees it.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 26a19ea699060fded98257e65b0ae5272a5ea1da
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:40 2015 +0100
usb: dwc2: host: fix use of qtd after free in desc dma mode
When completing non isoc xfer, dwc2_complete_non_isoc_xfer_ddma()
is relying on qtd->n_desc to process the corresponding number of
descriptors.
During the processing of these descriptors, qtd could be unlinked
and freed if xfer is done and urb is no more in progress.
In this case, dwc2_complete_non_isoc_xfer_ddma() will read again
qtd->n_desc whereas qtd has been freed. This will lead to unpredictable
results since qtd->n_desc is no more valid value.
To avoid this error, return a result != 0 in dwc2_process_non_isoc_desc(),
so that dwc2_complete_non_isoc_xfer_ddma() stops desc processing.
This has been seen with Slub debug enabled.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit c503b38153852d88774b54ae17f7723f68c6dc33
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:39 2015 +0100
usb: dwc2: host: rework isochronous halt path
When a channel is halted because of urb dequeue during transfer
completion, no other qtds must be scheduled until halt is done.
Moreover, all in progress qtds must be given back.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit dde4c1bf5df0f852e497e5644d3578885b969fdb
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:38 2015 +0100
usb: dwc2: host: set active bit in isochronous descriptors
Active bit must be enabled in all scheduled descriptors. Else transfer
never start.
Remove previous code which was not correctly configuring descriptors.
Active bit was set before calling dwc2_fill_host_isoc_dma_desc() which
is erasing dma_desc->status.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 3ac38d260fa5dc8ec26ee5b6f5330d726ec00065
Author: Gregory Herrero <gregory.herr...@intel.com>
Date: Thu Nov 5 09:41:37 2015 +0100
usb: dwc2: host: ensure filling of isoc desc is correctly done
Increment qtd->isoc_frame_index_last before testing it, else below
check will never be true and IOC (Interrupt On Complete) bit for
last frame will never be set in descriptor status.
/* Set IOC for each descriptor corresponding to last frame of URB */
if (qtd->isoc_frame_index_last == qtd->urb->packet_count)
dma_desc->status |= HOST_DMA_IOC;
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Gregory Herrero <gregory.herr...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit f74875dc36135ebae82a8e005f4b7f52289d2c40
Author: Stefan Wahren <stefan.wah...@i2se.com>
Date: Thu Nov 12 21:08:34 2015 +0000
usb: dwc2: fix kernel oops during driver probe
This patch make sure that all necessary members of dwc2_hsotg
are initialized before the irq handler is requested. So
the kernel oops triggered by dwc2_handle_common_intr has
been fixed.
dwc2 20980000.usb: Configuration mismatch. Forcing host mode
dwc2 20980000.usb: no platform data or transceiver defined
Unable to handle kernel paging request at virtual address cc860040
pgd = c0004000
[cc860040] *pgd=0b41e811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] ARM
CPU: 0 PID: 1 Comm: swapper Not tainted 4.3.0-rc3+ #19
Hardware name: BCM2835
task: cb494000 ti: cb4d0000 task.ti: cb4d0000
PC is at dwc2_is_controller_alive+0x18/0x34
LR is at dwc2_handle_common_intr+0x24/0xb60
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: Stefan Wahren <stefan.wah...@i2se.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 8aa90cf2a28645c6733f8879c5fe1848c5d510b7
Author: Stefan Wahren <stefan.wah...@i2se.com>
Date: Fri Nov 13 17:02:12 2015 +0000
usb: dwc2: make otg clk optional
Fixes commit 09a75e857790
("usb: dwc2: refactor common low-level hw code to platform.c")
The above commit consolidated the low-level phy access into a common
location. This change made the otg clk a requirement and broke some
platforms when it was moved into platform.c.
So make clk handling optional again.
Acked-by: Eric Anholt <e...@anholt.net>
Signed-off-by: Stefan Wahren <stefan.wah...@i2se.com>
Cc: Marek Szyprowski <m.szyprow...@samsung.com>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: Marek Szyprowski <m.szyprow...@samsung.com>
Fixes: 09a75e857790 ("usb: dwc2: refactor common low-level hw code to
platform.c")
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 6c2dad69163fdb4ea82344dcba360fc00b4adda4
Author: Stefan Wahren <stefan.wah...@i2se.com>
Date: Fri Nov 13 17:02:11 2015 +0000
usb: dwc2: Return errors from PHY
When searching for PHYs, any error was treated as if the PHY did not
exist or was not specified. Thus the probe function did not
correctly return error conditions such as -EPROBE_DEFER.
Fixed so that only a non-existing PHY is ignored and any other error
is returned.
Acked-by: Eric Anholt <e...@anholt.net>
Reported-by: Alexander Aring <alex.ar...@gmail.com>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Stefan Wahren <stefan.wah...@i2se.com>
Tested-by: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit d0464bcf12af54bafe02dd23ac5bd75d825f9fdd
Author: John Youn <john.y...@synopsys.com>
Date: Fri Nov 13 17:02:10 2015 +0000
usb: dwc2: Make PHY optional
Fixes commit 09a75e857790
("usb: dwc2: refactor common low-level hw code to platform.c")
The above commit consolidated the low-level phy access into a common
location. This change introduced a check from the gadget requiring
that a PHY is specified. This requirement never existed on the host
side and broke some platforms when it was moved into platform.c.
The gadget doesn't require the PHY either so remove the check.
Acked-by: Eric Anholt <e...@anholt.net>
Reported-by: Stefan Wahren <i...@lategoodbye.de>
Cc: Marek Szyprowski <m.szyprow...@samsung.com>
Signed-off-by: John Youn <johny...@synopsys.com>
Tested-by: Marek Szyprowski <m.szyprow...@samsung.com>
Fixes: 09a75e857790 ("usb: dwc2: refactor common low-level hw code to
platform.c")
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 1fb7f12d5bec1b0a699c85d724bd5184a01fa2dd
Author: Douglas Anderson <diand...@chromium.org>
Date: Thu Oct 22 13:05:03 2015 -0700
usb: dwc2: host: Fix remote wakeup when not in DWC2_L2
In commit 734643dfbdde ("usb: dwc2: host: add flag to reflect bus
state") we changed dwc2_port_suspend() not to set the lx_state
anymore (instead it sets the new bus_suspended variable). This
introduced a bug where we would fail to detect device insertions if:
1. Plug empty hub into dwc2
2. Plug USB flash drive into the empty hub.
3. Wait a few seconds
4. Unplug USB flash drive
5. Less than 2 seconds after step 4, plug the USB flash drive in again.
The dwc2_hcd_rem_wakeup() function should have been changed to look at
the new bus_suspended variable.
Let's fix it. Since commit b46146d59fda ("usb: dwc2: host: resume root
hub on remote wakeup") talks about needing the root hub resumed if the
bus was suspended, we'll include it in our test.
It appears that the "port_l1_change" should only be set to 1 if we were
in DWC2_L1 (the driver currently never sets this), so we'll update the
former "else" case based on this test.
Fixes: 734643dfbdde ("usb: dwc2: host: add flag to reflect bus state")
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: Gregory Herrero <gregory.herr...@intel.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit f16593034a30bcbef8f63c37d0f2b9e1a0902c2d
Author: Douglas Anderson <diand...@chromium.org>
Date: Tue Oct 20 16:33:53 2015 -0700
usb: dwc2: host: Fix ahbcfg for rk3066
The comment for ahbcfg for rk3066 parameters (also used for rk3288)
claimed that ahbcfg was INCR16, but it wasn't. Since the bits weren't
shifted properly, the 0x7 ended up being masked and we ended up
programming 0x3 for the HBstLen. Let's set it to INCR16 properly.
As per Wu Liang Feng at Rockchip this may increase transmission
efficiency. I did blackbox tests with writing 0s to a USB-based SD
reader (forcefully capping CPU Freq to try to measure efficiency):
cd /sys/devices/system/cpu/cpu0/cpufreq
echo userspace > scaling_governor
echo 126000 > scaling_setspeed
for i in $(seq 10); do
dd if=/dev/zero of=/dev/sdb bs=1M count=750
done
With the above tests I found that speeds went from ~15MB/s to ~18MB/s.
Note that most other tests I did (including reading from the same USB
reader) didn't show any difference in performance.
Tested-by: Heiko Stuebner <he...@sntech.de>
Acked-by: John Youn <johny...@synopsys.com>
Reviewed-by: Liangfeng Wu <w...@rock-chips.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit dc8730846948e517169f630826cd2c97615f5ee8
Author: Doug Anderson <diand...@chromium.org>
Date: Fri Oct 16 16:01:32 2015 -0700
usb: dwc2: host: Fix use after free w/ simultaneous irqs
While plugging / unplugging on a DWC2 host port with "slub_debug=FZPUA"
enabled, I found a crash that was quite obviously a use after free.
It appears that in some cases when we handle the various sub-cases of
HCINT we may end up freeing the QTD. If there is more than one bit set
in HCINT we may then end up continuing to use the QTD, which is bad.
Let's be paranoid and check for this after each sub-case. This should
be safe since we officially have the "hsotg->lock" (it was grabbed in
dwc2_handle_hcd_intr).
The specific crash I found was:
Unable to handle kernel paging request at virtual address 6b6b6b9f
At the time of the crash, the kernel reported:
(dwc2_hc_nak_intr+0x5c/0x198)
(dwc2_handle_hcd_intr+0xa84/0xbf8)
(_dwc2_hcd_irq+0x1c/0x20)
(usb_hcd_irq+0x34/0x48)
Popping into kgdb found that "*qtd" was filled with "0x6b", AKA qtd had
been freed and filled with slub_debug poison.
kgdb gave a little better stack crawl:
0 dwc2_hc_nak_intr (hsotg=hsotg@entry=0xec42e058,
chan=chan@entry=0xec546dc0, chnum=chnum@entry=4,
qtd=qtd@entry=0xec679600) at drivers/usb/dwc2/hcd_intr.c:1237
1 dwc2_hc_n_intr (chnum=4, hsotg=0xec42e058) at
drivers/usb/dwc2/hcd_intr.c:2041
2 dwc2_hc_intr (hsotg=0xec42e058) at drivers/usb/dwc2/hcd_intr.c:2078
3 dwc2_handle_hcd_intr (hsotg=0xec42e058) at
drivers/usb/dwc2/hcd_intr.c:2128
4 _dwc2_hcd_irq (hcd=<optimized out>) at drivers/usb/dwc2/hcd.c:2837
5 usb_hcd_irq (irq=<optimized out>, __hcd=<optimized out>) at
drivers/usb/core/hcd.c:2353
Popping up to frame #1 (dwc2_hc_n_intr) found:
(gdb) print /x hcint
$12 = 0x12
AKA:
#define HCINTMSK_CHHLTD (1 << 1)
#define HCINTMSK_NAK (1 << 4)
Further debugging found that by simulating receiving those two
interrupts at the same time it was trivial to replicate the
use-after-free. See <http://crosreview.com/305712> for a patch and
instructions. This lead to getting the following stack crawl of the
actual free:
0 arch_kgdb_breakpoint () at arch/arm/include/asm/outercache.h:103
1 kgdb_breakpoint () at kernel/debug/debug_core.c:1054
2 dwc2_hcd_qtd_unlink_and_free (hsotg=<optimized out>, qh=<optimized
out>, qtd=0xe4479a00) at drivers/usb/dwc2/hcd.h:488
3 dwc2_deactivate_qh (free_qtd=<optimized out>, qh=0xe5efa280,
hsotg=0xed424618) at drivers/usb/dwc2/hcd_intr.c:671
4 dwc2_release_channel (hsotg=hsotg@entry=0xed424618,
chan=chan@entry=0xed5be000, qtd=<optimized out>,
halt_status=<optimized out>) at drivers/usb/dwc2/hcd_intr.c:742
5 dwc2_halt_channel (hsotg=0xed424618, chan=0xed5be000, qtd=<optimized
out>, halt_status=<optimized out>) at
drivers/usb/dwc2/hcd_intr.c:804
6 dwc2_complete_non_periodic_xfer (chnum=<optimized out>,
halt_status=<optimized out>, qtd=<optimized out>, chan=<optimized
out>, hsotg=<optimized out>) at drivers/usb/dwc2/hcd_intr.c:889
7 dwc2_hc_xfercomp_intr (hsotg=hsotg@entry=0xed424618,
chan=chan@entry=0xed5be000, chnum=chnum@entry=6,
qtd=qtd@entry=0xe4479a00) at drivers/usb/dwc2/hcd_intr.c:1065
8 dwc2_hc_chhltd_intr_dma (qtd=0xe4479a00, chnum=6, chan=0xed5be000,
hsotg=0xed424618) at drivers/usb/dwc2/hcd_intr.c:1823
9 dwc2_hc_chhltd_intr (qtd=0xe4479a00, chnum=6, chan=0xed5be000,
hsotg=0xed424618) at drivers/usb/dwc2/hcd_intr.c:1944
10 dwc2_hc_n_intr (chnum=6, hsotg=0xed424618) at
drivers/usb/dwc2/hcd_intr.c:2052
11 dwc2_hc_intr (hsotg=0xed424618) at drivers/usb/dwc2/hcd_intr.c:2097
12 dwc2_handle_hcd_intr (hsotg=0xed424618) at
drivers/usb/dwc2/hcd_intr.c:2147
13 _dwc2_hcd_irq (hcd=<optimized out>) at drivers/usb/dwc2/hcd.c:2837
14 usb_hcd_irq (irq=<optimized out>, __hcd=<optimized out>) at
drivers/usb/core/hcd.c:2353
Though we could add specific code to handle this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 4d273c2af0fe4fdc84eef27e4521694dc7992065
Author: Douglas Anderson <diand...@chromium.org>
Date: Wed Oct 14 15:58:27 2015 -0700
usb: dwc2: host: Protect PCGCTL with lock in dwc2_port_resume()
From code inspection, it appears to be unsafe to do a read-modify-write
of PCGCTL in dwc2_port_resume(). Let's make sure the spinlock is held
around this operation.
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 09a75e8577901489f77a14a3b305a9a1f67bf25b
Author: Marek Szyprowski <m.szyprow...@samsung.com>
Date: Wed Oct 14 08:52:29 2015 +0200
usb: dwc2: refactor common low-level hw code to platform.c
DWC2 module on some platforms needs three additional hardware
resources: phy controller, clock and power supply. All of them must be
enabled/activated to properly initialize and operate. This was initially
handled in s3c-hsotg driver, which has been converted to 'gadget' part
of dwc2 driver. Unfortunately, not all of this code got moved to common
platform code, what resulted in accessing DWC2 registers without
enabling low-level hardware resources. This fails for example on Exynos
SoCs. This patch moves all the code for managing those resources to
common platform.c file and provides convenient wrappers for controlling
them.
Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 758ed196fcc4373a129fd661875af52d7e7d4e73
Author: Marek Szyprowski <m.szyprow...@samsung.com>
Date: Wed Oct 14 08:52:28 2015 +0200
usb: dwc2: remove no longer needed init_mutex
init_mutex is a leftover from the time, when s3c-hsotg driver did not
implement proper pull up/down control and emulated it by enabling
enabling/disabling usb phy. Proper pull up/down control has been added
by commit 5b9451f8c4fbaf0549139755fb45ff2b57975b7f ("usb: dwc2: gadget:
use soft-disconnect udc feature in pullup() method"), so init_muxtex can
be removed now to avoid potential deadlocks with other locks.
Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit 44e4a60dacf8a96f28b5e021b54ba9eeb793ca2e
Author: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Date: Mon Oct 12 11:23:27 2015 +0200
usb: dwc2: fix duplicate argument warning
Fix a duplicate argument warning reported by 0-DAY kernel test
infrastructure in the following patch:
77dbf71 usb: dwc2: host: add disconnect interrupt to host only interrupts
Acked-by: John Youn <johny...@synopsys.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kau...@intel.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
commit ec1f9d9f01384fe656a6f92b90de274146fe35a1
Author: Roman Bacik <rba...@broadcom.com>
Date: Thu Sep 10 18:13:43 2015 -0700
usb: dwc2: gadget: parity fix in isochronous mode
USB OTG driver in isochronous mode has to set the parity of the receiving
microframe. The parity is set to even by default. This causes problems for
an audio gadget, if the host starts transmitting on odd microframes.
This fix uses Incomplete Periodic Transfer interrupt to toggle between
even and odd parity until the Transfer Complete interrupt is received.
Signed-off-by: Roman Bacik <rba...@broadcom.com>
Reviewed-by: Abhinav Ratna <ara...@broadcom.com>
Reviewed-by: Srinath Mannam <srinath.man...@broadcom.com>
Signed-off-by: Scott Branden <sbran...@broadcom.com>
Signed-off-by: John Youn <johny...@synopsys.com>
Signed-off-by: Felipe Balbi <ba...@ti.com>
Status:
Vendor Tag: SYNOPSYS
Release Tags: dwc2-2016-02-14
C src/sys/external/bsd/dwc2/dist/dwc2_core.c
C src/sys/external/bsd/dwc2/dist/dwc2_core.h
C src/sys/external/bsd/dwc2/dist/dwc2_coreintr.c
C src/sys/external/bsd/dwc2/dist/dwc2_hcd.c
C src/sys/external/bsd/dwc2/dist/dwc2_hcd.h
C src/sys/external/bsd/dwc2/dist/dwc2_hcdddma.c
C src/sys/external/bsd/dwc2/dist/dwc2_hcdintr.c
C src/sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c
C src/sys/external/bsd/dwc2/dist/dwc2_hw.h
9 conflicts created by this import.
Use the following command to help the merge:
cvs checkout -jSYNOPSYS:yesterday -jSYNOPSYS
src/sys/external/bsd/dwc2/dist
