Module Name: src
Committed By: macallan
Date: Fri Jan 29 01:54:14 UTC 2016
Modified Files:
src/sys/arch/evbmips/conf: CI20 files.ingenic
src/sys/arch/evbmips/ingenic: clock.c intr.c machdep.c mainbus.c
Added Files:
src/sys/arch/evbmips/ingenic: cpu.c cpu_startup.S
Log Message:
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/evbmips/conf/CI20
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/conf/files.ingenic
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/clock.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/ingenic/cpu.c \
src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbmips/ingenic/intr.c \
src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/mainbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
