Module Name: src
Committed By: bouyer
Date: Sat Oct 17 14:46:01 UTC 2015
Modified Files:
src/sys/arch/arm/allwinner: awin_board.c
Log Message:
awin_cpu_clk(): Fix reading of CPU_CLK_SRC_CEL bits: doing a shiftin followed
by a shiftout ends up reading bits(0,1) instead of AWIN_CPU_CLK_SRC_SEL.
It happens that these bits (AWIN_AXI_CLK_DIV_RATIO) are 2 (divide by 3) at boot
(at last on cubieboard2 and olimex lime2), which matches
AWIN_CPU_CLK_SRC_SEL_PLL1, so this has gone unnoticed.
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/allwinner/awin_board.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
