Module Name: src Committed By: macallan Date: Tue Dec 23 16:16:49 UTC 2014
Modified Files:
src/sys/arch/evbmips/conf: CI20 files.ingenic
Log Message:
more debug defflag-ing
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/conf/CI20
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/conf/files.ingenic
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
