Module Name: src Committed By: kiyohara Date: Thu May 19 07:51:50 UTC 2011
Modified Files: src/sys/arch/powerpc/ibm4xx: 4xx_trap_subr.S Log Message: + Load TLB-miss-address from SRR0, if ITMISS. + Remove a white space. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/powerpc/ibm4xx/4xx_trap_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.