Module Name: src
Committed By: jruoho
Date: Wed Feb 23 06:17:55 UTC 2011
Modified Files:
src/sys/dev/acpi: acpi_cpu_pstate.c acpi_cpu_tstate.c
Log Message:
Lower the worst-case latency in P- and T-state transitions to 1 usec.
The previous 10 usec was based on the Intel's Core family. It may have been
improved since that. Also provide an arbitrary upper bound for BIOS bugs.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/dev/acpi/acpi_cpu_pstate.c
cvs rdiff -u -r1.20 -r1.21 src/sys/dev/acpi/acpi_cpu_tstate.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
