Module Name: src
Committed By: msaitoh
Date: Thu Dec 24 15:51:04 UTC 2020
Modified Files:
src/sys/dev/pci/ixgbe: ixgbe.c
Log Message:
The EICR register's all OTHER interrupt bits are cleared in the beginning of
the ixgbe_msix_admin(), so it's not required to clear each bit later in the
function.
To generate a diff of this commit:
cvs rdiff -u -r1.266 -r1.267 src/sys/dev/pci/ixgbe/ixgbe.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
