Module Name: src
Committed By: jmcneill
Date: Sun Nov 1 12:13:21 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with
subsequent wfi/wfe instructions. Haven't seen this in practice but I would
rather be safe here.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
