Module Name: src Committed By: rin Date: Wed Jul 15 09:16:35 UTC 2020
Modified Files:
src/sys/arch/powerpc/fpu: fpu_emu.c
Log Message:
Do not raise SIGFPE unless MSR[FE0] or MSR[FE1] is set via fenv(3).
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/powerpc/fpu/fpu_emu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
