Module Name: src Committed By: ad Date: Wed May 20 20:19:02 UTC 2020
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
The boot CPU suffers a cache miss during TSC sync, before RDTSC. Make the
secondary CPU take a miss as well to try and delay it an equal amount.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/x86/x86/tsc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
